Full-wave coupled inductor power converter having...

Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter

Reexamination Certificate

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Reexamination Certificate

active

06765810

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to DC-DC power conversion.
2. Background of the Invention
DC-DC power converters are power-processing circuits that convert an unregulated DC input voltage to a regulated DC output voltage, usually at a different level, for powering a load. A vast variety of topologies for DC-DC converters have been introduced over the years, but not all are suitable for delivering the low voltage and high current outputs that are now required by microprocessor, memory and other integrated circuit loads. Further, the need for small size and high efficiency places additional limitations on the available topologies. Small size equates to high power density, and power density is the ratio of output power capability to converter volume.
To achieve high power density, the power loss must be low, or the operating temperature will increase, and additional thermal management devices, such as heatsink dissipators, may be required. The use of such devices defeats the objective to obtain high power density. To avoid heatsinks under normal operating conditions, the conduction losses must be minimized, and synchronous rectifiers have been shown to greatly improve rectification efficiency.
Synchronous rectifiers require a control signal to drive the device to a low resistance state and provide very low loss conduction, but they also include an internal diode, which can conduct current, albeit with higher losses. A proper control strategy is needed to ensure that the internal diode does not conduct. Synchronous rectifiers can also conduct in reverse, and this could produce a short circuit, so the controlling circuit must be carefully designed.
A fundamental DC-DC power conversion topology is the single-ended forward converter shown in
FIG. 1
a
. This topology, when controlled by a constant frequency, pulse-width-modulation (PWM) control circuit
10
, provides excellent regulation and fast response time. In operation, the primary switch
11
is turned ON to apply the source voltage V
in
to the transformer
12
. Immediately, a secondary voltage appears, and current flows simultaneously in the primary winding
13
and secondary winding
14
, and energy is transferred forward. The secondary load current flows through diode
15
, and diode
16
is reverse biased at this time. The difference between the secondary winding voltage and the output voltage V
out
appears across the filter inductor
17
, and energy is stored in the inductor
17
during this ON period. In addition, the inductor
17
limits the rate of change of current during the ON period.
When switch
11
is turned OFF, the current in the secondary winding
14
vanishes, but load current continues to flow through diode
16
and inductor
17
, and the stored energy in the inductor
17
provides continuity of current to the filter capacitor
18
and output V
out
. The current in the transformer primary winding
13
also vanishes except for a small amount of magnetizing current. Various methods have been disclosed to reset the transformer core during the OFF period, and these are well known to those skilled in the art. The primary and secondary winding voltages will reverse during reset, and diode
15
is reverse biased disconnecting the load (not shown) from the transformer
12
.
The single-ended circuit of
FIG. 1
a
is not optimal, and one deficiency is that energy for the entire switching cycle must be drawn from the source (V
in
) during the ON period of the primary switch
11
, and an equivalent period of time is required for the OFF period of the primary switch to allow the core to reset. The single pulse of high current followed by a long dead time results in a high RMS current and excessive conduction loss in the primary circuit, thus limiting the topology to low power applications. Furthermore, the output voltage V
out
is the average value of the pulsed waveform that appears on the secondary winding
14
, and due to the extended dead time, each rectifier (i.e., diodes
15
,
16
) experiences a peak reverse voltage much higher than the average. Because rectification is only accomplished approximately half of the time, i.e. during the ON period of the primary switch, the topology is known as half-wave.
These deficiencies are almost entirely removed by the double-ended topology of
FIG. 1
b
. The double-ended topology operates much like two overlapping single ended circuits and has similar control and response characteristics. The power converter of
FIG. 1
b
includes a second primary switch
21
, which is controlled ON during the time switch
20
is OFF. In operation, switch
20
first connects the primary winding
22
to input capacitor
23
, and then switch
21
connects the same winding
22
to input capacitor
24
. This results in an alternating voltage across the primary winding
22
. The voltage across each of the input capacitors
23
,
24
will be one-half the source voltage V
in
.
Energy is transferred to the secondary windings
26
,
27
during the ON period of each primary switch
20
,
21
, and the core flux, which increases during the first ON period, is reset during the subsequent ON period. A dead time for reset is not required. However, dead time may be used along with a PWM regulation technique, provided by PWM control circuit
25
. This control time can be varied from zero to a full half-cycle. With a double-ended topology, two current pulses of lower magnitude are drawn from the source during each switching cycle, and the primary winding
22
carries bipolar current with an improved RMS value.
The half-bridge topology of
FIG. 1
b
is shown with two secondary windings
26
,
27
, and each is connected to one of the rectifying diodes
28
,
29
. The diodes
28
,
29
alternately conduct current from their respective secondary windings
26
,
27
when they are forward biased, and the rectification is known as full-wave. The more continuous current to the output V
out
reduces the requirement for energy storage during any dead time which may occur, and the inductor
30
consequently may be made smaller.
One known variation to these topologies is to translate the filter inductor to the primary circuit. A single ended circuit according to this variation is shown in
FIG. 2
, and the core reset mechanism is not shown. The primary winding
32
and inductor winding
33
now carry primary current, which is typically less than load current. In addition, as before, the inductor
33
stores energy during the ON period of the primary switch
31
. However, to permit discharge of this energy during the OFF period, a second winding
35
must be added to the inductor and connected through a diode
37
to the output V
out
. Effectively, the inductor has become a second flyback transformer with its primary
33
connected in series with the primary winding
32
of the first transformer
39
. The ratio of the primary
33
to secondary
35
turns on the inductor may be identical to the ratio of the primary
32
to secondary
34
turns on the transformer
39
.
With the filter inductor
33
located in the primary circuit the input voltage drops across it, and a reduced voltage is applied to the transformer
39
. In operation, the secondary windings
34
,
35
, and diodes,
36
,
37
are connected directly to the output voltage V
out
, and the winding and reverse diode voltages are limited to the magnitude of the output voltage V
out
. A constant frequency PWM control technique can be applied to the primary switch
31
to regulate the output voltage V
out
. Double-ended topologies pursuant to this variation, including a half-bridge type that is analogous to
FIG. 1
b
, are also known.
Still, none of the above topologies define a suitable control method when synchronous rectifiers are used to reduce rectification losses. Accordingly, there exists a need in the art for a power conversion topology and control technique that is compatible with synchronous rectification and yet capable of satisfying the requirements for high power density and low voltage, high

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