Full subtracter

Details Full subtracter Full subtracter

1996-08-22

1998-12-08

Sheikh, Ayaz R.

Boots, shoes, and leggings

G06F 7385

Patent

active

058479830

ABSTRACT:
An improved full subtracter is disclosed which receives a minuend signal A having a weight of +1, a subtrahend signal B having a weight of -1 and a borrow input signal Xi having a weight of -1 and provides a difference output: signal D having a weight of +1 and a borrow output signal Xo having a weight of -2. The full subtracter is composed of CMOS transistors such that both the signal D delay time and the signal Xo delay time are decreased by reducing the number of logic gate stages.

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patent: 4912345 (1990-03-01), Steele et al.
patent: 5079450 (1992-01-01), Win et al.

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