Full-rail, dual-supply global bitline accelerator CAM circuit

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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C365S189060

Reexamination Certificate

active

07426127

ABSTRACT:
A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

REFERENCES:
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patent: 2005/0073879 (2005-04-01), Gogl et al.
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patent: 2005/0237805 (2005-10-01), Matsuzaki et al.
patent: 2007/0035992 (2007-02-01), Curatolo et al.
Agarwal et al. “A Dual-Supply 4GHz 13fJ/bit/search 64x128b CAMin 65nm CMOS” 1-4244-0303-4/06, 2006 IEEE pp. 303-306.

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