Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2008-09-16
2008-09-16
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189060
Reexamination Certificate
active
11642838
ABSTRACT:
A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.
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Agarwal Amit
Hsu Steven
Krishnamurthy Ram
Intel Corporation
Ked & Associates LLP
Tran Michael T
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