Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-02-25
2001-12-04
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000, C365S230060
Reexamination Certificate
active
06327216
ABSTRACT:
RELATED APPLICATIONS
This application is a continuation in part of a patent application filed.
FIELD OF THE INVENTION
This invention relates generally to dual-data rate (DDR) memories, and more particularly to full page increment/decrement burst for such memories.
BACKGROUND OF THE INVENTION
Graphics-intensive applications for computers such as personal computers (PC's) are becoming increasingly more popular. Such applications include high-end computer-aided drafting (CAD) applications, games, real-time video applications, as well as other applications. As these applications become more complex, they require the computers on which they are run to render and execute graphics much more quickly. Furthermore, as the typical resolution of computer screens have increased from 640×480 pixels (horizontal×vertical) to 800×600, 1024×768 and beyond, and increased color information per pixel from two bits to 24 bits to 32 bits and beyond, the processing demand placed on the computers for fast graphics execution has also grown.
The typical computer relies on a graphics subsystem (also known as a graphics card, video card, graphic accelerator card, or a display adapter, among other terms) to assist it in the display of graphics on a display device. A graphics card generally includes a specialized processor or processors that are tailor-made for graphics rendering, as well as an amount of memory, ranging from one, two, four, eight, sixteen megabytes and up, so that a complete screen of graphics information, known as a frame, can be stored by the graphics card. Thus, this memory is generally known as a frame buffer of the graphics card. Graphics “cards”, may also be integrated within a single chip on a motherboard of a computer. A graphics card, and potentially other components, make up the graphics subsystem of a computer. The entirety of the graphics subsystem may also be integrated into a single chip on the motherboard of a computer. The graphic subsystem and other computer components from the motherboard may alternatively be embedded in a semiconductor chip.
Initially, the memory of a graphics card was standard-issue dynamic random-access memory (DRAM), of a sort also used by computer processors to hold more general information. Thus, as improvements in memory to increase their speed became available, such as the introduction of synchronous dynamic random-access memory (SDRAM), they usually have been utilized within graphics cards, too. Ultimately, however, the specialized needs of graphics rendering required their own type of memory, such as synchronous graphics random-access memory (SGRAM), which is analogous to SDRAM, but includes enhanced graphics features for use with graphics cards. The need for faster memory within graphics cards has not, however, abated.
Thus, graphics cards manufacturers have looked to new technologies, such as Rambus DRAM's (also known as Direct RDRAM's), available from Rambus, Inc. of Mountain View, Calif., to increase graphics subsystem performance. Rambus DRAM use within graphics cards, however, has been limited because it is based on a closed standard governed by Rambus, Inc., such that use of Rambus DRAM requires the payment of royalties to Rambus, Inc. Therefore, manufacturers have looked to other technologies that are based on open standards.
One such type of memory is the Double Data Rate (DDR) DRAM. The DDR DRAM achieves increased performance by providing for two data accesses within a single clock cycle —hence its name —by enabling the memory to read data on both the rising and falling edges of each clock cycle. The concept of DDR memories has been extended to SDRAM's and SGRAM's in particular, resulting in DDR SDRAM and DDR SGRAM. Such memory has witnessed increased interest on the part of graphics card designers as a manner by which increased graphics performance can be realized.
A disadvantage to DDR SDRAM/SGRAM's found in the prior art, however, is that full-page burst is not generally provided for. (In general, a burst operation for a memory is defined as an operation retrieving a given number of data stored at sequential locations within the memory (e.g., a full-page of memory), which ultimately allows the data to be retrieved in a faster manner —hence the term “burst.”) This is because of a limitation of the prefetch nature of DDR devices. That is, in a DDR device, for a given clock cycle, two words of data, each of n-bits length, are retrieved, such that both must be from the same location within the memory as addressed by the logical circuitry before the next location can be moved to. This is acceptable for a full-page increment burst starting with an even start word address, because the second data word retrieved is still within the same location within the memory as the first data word. However, a full-page increment burst starting with an odd start word address does not work, because the second data word retrieved will necessarily not lie within the same location as the first data word as addressed by the logical circuitry, violating the limitation of the prefetch nature of DDR devices.
There is a need, therefore, for a DDR SDRAM/SGRAM that has burst capability. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification. The invention relates to a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.
Thus, the invention provides for advantages not found in the prior art. A DDR SDRAM/SGRAM according to the invention is able to have a burst increment mode when starting at an even word address, and a burst decrement mode when starting at an odd word address. Thus, the limitation imposed by the prefetch nature of DDR devices is not violated. When starting at an even word address, the DDR SDRAM/SGRAM counts up (increments) so that the second data word retrieved is still from the same memory location as the first data word as addressed by the logic circuitry, while when starting at an odd word address, the DDR SDRAM/SGRAM counts down (decrements), also so that the second data word retrieved is still from the same memory location as the first data word as addressed by the logic circuitry.
The invention includes DDR SDRAM/SGRAM's, memory devices, graphics subsystems, graphics cards and computers whether formed from component semiconductor chips or embedded on a semiconductor chip. It also includes methods of varying scope. Still other embodiments, advantages and aspects of the invention will be understood by reference to the drawings and by reading the detailed description.
REFERENCES:
patent: 5644788 (1997-07-01), Courtright et al.
patent: 5915126 (1999-06-01), Maule et al.
patent: 5973993 (1999-10-01), Morgan
patent: 6011751 (2000-01-01), Hirabayashi
“16Mb Double Data Rate Synchronous Graphics RAM”,IBM Corporation,IBM01616328RL6A, pp. 1-53, (Dec. 1997).
“16Mbit DDR SGRAM, 128K×32Bit×4 Banks Double Data Rate Synchronous Graphic RAM with Bi-directional Data Strobe, Revision 0.6”,Samsung Electronics,KM432D5131, pp. 1-48, (Apr. 1998).
Le Vu A.
Micro)n Technology, Inc.
Schwegman, Lungberg, Woessner & Kluth P.A.
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