Full output voltage driver circuit using bootstrap capacitor and

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307482, 307270, 307605, H03K 424, H03K 1706, H03K 17687, H03K 19094

Patent

active

045462763

ABSTRACT:
An MOS driver circuit which provides full VDD and VSS output logic levels uses a bootstrap capacitor and a delay circuit whose delay is controlled by potential of the terminal which is bootstrapped. Adverse effects of processing variations are limited because the delay time of the delay circuit is determined by the components which selectively control the potential of the bootstrapped terminal.

REFERENCES:
patent: 4071783 (1978-01-01), Knepper
patent: 4276487 (1981-06-01), Arzubi et al.
patent: 4291242 (1981-09-01), Schriber
patent: 4317051 (1982-02-01), Young, Jr.
patent: 4342928 (1982-08-01), Gschwendtner et al.

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