Full-level, fast CMOS output buffer

Details Full-level, fast CMOS output buffer Full-level, fast CMOS output buffer

1988-02-11

1989-04-25

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307263, 307446, 307451, H03K 19094, H03K 17284, H03K 1920

Patent

active

048251011

ABSTRACT:
An output buffer includes a pull-up circuit and a pull-down circuit for driving widely varying capacitive and inductive loads without significant output ringing. The pull-up circuit includes a first pull-up transistor (N2), a NAND logic gate (42) and a second pull-up transistor (P2). The pull-down circuit includes a first pull-down transistor (P3), a NOR logic gate (38) and a second pull-down transistor (N3). Output impedance is increased and energy stored in parasitic inductance is decreased by the pull-up and pull-down transistors so as to reduce significantly the inductive ringing while accelerating output transitions.

REFERENCES:
patent: 4540904 (1985-09-01), Ennis et al.
patent: 4567378 (1986-01-01), Raver
patent: 4684824 (1987-08-01), Moberg
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4749882 (1988-06-01), Morgan
patent: 4769561 (1988-09-01), Iwamura et al.
patent: 4779014 (1988-10-01), Masuoka et al.

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