Full duplex buffer management and apparatus

Details Full duplex buffer management and apparatus Full duplex buffer management and apparatus

1996-02-22

2000-05-23

Harrell, Robert B.

395250, H01J 100

Patent

active

060674083

ABSTRACT:
A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.

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