Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2000-08-10
2002-02-05
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S108000
Reexamination Certificate
active
06344768
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to DC-to-DC converters in general, and in particular to full-bridge DC-to-DC converters. Still more particularly, the present invention relates to a full-bridge DC-to-DC converter having an unipolar gate drive.
2. Description of the Prior Art
A direct current (DC) voltage can be converted to another DC voltage via a DC-to-DC converter. The basic topology of a DC-to-DC converter may take a variety of forms, such as a full-bridge inverter, a half-bridge inverter, a buck converter, a boost converter, or a flyback converter. Each topology is better suited for a specific type of application. For example, a boost converter topology is typically used when the desired output DC voltage needs to be greater than the input voltage, while a buck converter topology is typically used when the output voltage needs to be less than the input voltage. Generally, for low-power applications, i.e., below 50 watts, the buck, boost, or flyback converter topologies are more preferable, while for high-power applications, i e., above 50 watts, the half-bridge or full-bridge inverters topologies are more preferable.
Referring now to the drawings and in particular to
FIG. 1
, there is depicted a circuit diagram of a full-bridge DC-to-DC converter according to the prior art. As shown, a DC-to-DC converter
10
converts an input voltage +Vd (relative to a ground voltage of 0 V) at DC input terminals
11
to a desired output voltage at DC output terminals
12
intended for supplying to a load (not shown). control circuit (not shown) supplies pulsed control signals G
1
to G
4
to switching transistors
51
-
54
for maintaining the output voltage at its desired level using phase shift control in a well-known manner. The pulsed control signals G
1
and G
2
are generally complementary to one another at a desired switching frequency, and the pulsed control signals G
3
and G
4
are relatively variably phase shifted from the pulsed control signals G
1
and G
2
to provide the phase shift control. The switching frequency is typically desired to be high to permit DC-to-DC converter
10
to be implemented using components of relatively small size.
DC-to-DC converter
10
also includes a transformer
14
having a primary winding
16
and a center tapped secondary winding
18
, the senses of which are represented conventionally in
FIG. 1
by dots adjacent to the windings. The center tap of secondary winding
18
is connected to ground, and the outer ends of secondary winding
18
are connected to output terminals
12
via respective diodes
55
,
56
and an output filter. The output filter is an LC filter comprising a series output inductor
15
and a shunt output capacitor
19
.
Primary winding
16
is connected in series with an inductor
17
between the junction points of two switching legs, referred to as leg A and leg B, of a full bridge arrangement of switching transistors
51
to
54
controlled by the control signals G
1
to G
4
, respectively. Each of switching transistors
51
-
54
is constituted by the drain-source path of an n-channel MOSFET, which is illustrated with its parasitic or body diode connected in parallel with the drain-source path, to the gate of which the respective control signal is supplied. Snubber capacitors
61
to
64
are connected in parallel with the drain-source paths of switching transistors
51
to
54
. Switching leg A comprises switching transistors
51
and
52
connected in series between DC supply terminals
11
, and switching leg B comprises switching transistors
53
and
54
connected in series between DC supply terminals
11
, with the drains of the MOSFETs constituting switching transistors
51
and
53
being connected to the +Vd terminal and the sources of the MOSFETs constituting switching transistors
52
and
54
being connected to the ground terminal.
Snubber capacitors
61
to
64
are intended, in conjunction with inductor
17
, to provide for zero voltage switching (ZVS) to switching transistors
51
-
54
. In other words, each snubber capacitor is intended to be fully discharged at each switching time of the respective switching transistor, so that switching power losses are reduced. While this can be relatively closely approximated for the maximum or full-load, connected to output terminals
12
, for which DC-to-DC converter
10
is designed, at reduced and/or zero loads the snubber capacitors are not fully discharged at the turn-on times of the respective switches, and remaining energy stored in the snubber capacitors is dissipated in switching transistors
51
-
54
at turn-on. This results in increased switching losses with reduced loads, lower efficiency, and higher electromagnetic influence (EMI). In addition, the provision of inductor
17
in series with primary winding
16
results in an overlap in conduction of diodes
55
and
56
, and consequently reduces the power transfer from input terminals
11
to output terminals
12
. As a result, the effective duty cycle of DC-to-DC converter
10
is reduced.
Consequently, it would be desirable to provide an improved full-bridge DC-to-DC converter with more effective duty cycles.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a DC-to-DC converter includes a primary-to-secondary transformer, multiple gate drive circuits, and multiple gate drive transformers. The primary-to-secondary transformer converts a first DC voltage to a second DC voltage under the control of the gate drive circuits. Each of the gate drive circuits includes a first transistor and a second transistor. The gate of the first transistor is connected to a pulse voltage source via a diode. The drain of the second transistor is connected to the source of the first transistor, and the source of the second transistor is connected to the gate of the first transistor via a resistor, for discharging a gate-to-source voltage of the first transistor during the time when a voltage of the pulse voltage source is below a gate-to-source threshold voltage of the first transistor. Coupled to at least two of the gate drive circuits, each of the gate drive transformers controls at least two gate drive circuits.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4481434 (1984-11-01), Janutka
patent: 4500801 (1985-02-01), Janutka
patent: 4748351 (1988-05-01), Barzegar
patent: 4970420 (1990-11-01), Billings
patent: 5352932 (1994-10-01), Tihanyi
patent: 5404059 (1995-04-01), Loffler
patent: 5594378 (1997-01-01), Kruse et al.
patent: 5963078 (1999-10-01), Wallace
patent: 6271708 (2001-08-01), Hoshi et al.
Daun-Lindberg Timothy Charles
Miller Michael Lee
Bracewell & Patterson
International Business Machines - Corporation
Zweizig Jeffrey
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