Full address and odd boundary direct memory access controller wh

Details Full address and odd boundary direct memory access controller wh Full address and odd boundary direct memory access controller wh

1989-02-07

1993-05-25

Lee, Thomas C.

Boots, shoes, and leggings

3649691, 3649663, 36496433, 364963, 364DIG2, G06F 1202

Patent

active

052147673

ABSTRACT:
A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

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IBM Corp., Personal System/2 Model 80 Technical Reference, First Edition, Apr. 1987, pp. 3-15 to 3-27.

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