Full adder using NMOS transistor

Details Full adder using NMOS transistor Full adder using NMOS transistor

1996-12-27

1999-05-18

Ngo, Chuong Dinh

Boots, shoes, and leggings

36478403, 36478405, G06F7/50

Patent

active

059056673

ABSTRACT:
A full adder includes a static logic block for generating an inverted carry with respect to multiple inputs through an inverted carry output node; a first dynamic inverter logic block for inverting the inverted carry produced from the static logic block via the inverted carry output node according to a clock, to thereby generate a carry through a carry output node; a dynamic logic block for generating an inverted sum with respect to the multiple inputs according to an inverted clock via an inverted sum output node; and a second dynamic inverter logic block for inverting the inverted sum generated from the dynamic logic block via the inverted sum output node according to a clock, to thereby generate a sum through a sum output node.

REFERENCES:
patent: 4817030 (1989-03-01), Lee et al.
patent: 5140246 (1992-08-01), Rarick
patent: 5406506 (1995-04-01), Jiasheng et al.
patent: 5491653 (1996-02-01), Taborn et al.
patent: 5719803 (1998-02-01), Naffziger

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