Full adder circuit using differential transistor pairs

Details Full adder circuit using differential transistor pairs Full adder circuit using differential transistor pairs

1985-03-26

1988-04-26

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

047409070

ABSTRACT:
A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

REFERENCES:
patent: 3519810 (1970-07-01), Priel et al.
patent: 3906211 (1975-09-01), Glasser
patent: 3906212 (1975-09-01), Poguntke
patent: 3925651 (1975-12-01), Miller
patent: 4215418 (1980-07-01), Muramatsu
patent: 4569032 (1986-02-01), Lee
patent: 4583192 (1986-04-01), Cieslak

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