Full adder circuit

Details Full adder circuit Full adder circuit

1990-08-28

1992-05-26

Mai, Tan V.

Boots, shoes, and leggings

364788, G06F 750

Patent

active

051173867

ABSTRACT:
To generate quickly the several carry signals in a full adder circuit (for example a 40-bit circuit), the circuit is divided into a plurality of sub-circuits of a first type, in which complementary imaginary carry signals are generated parallel to each other. Carry look-ahead circuits are of a dual construction, each first carry look-ahead circuit receiving a logic "0" and each second carry look-ahead circuit receiving a login "1". So the generated imaginary carry signals are complementary, from which the carry signal proper is selected with the aid of a multiplex switch. The multiplex switch is controlled by the carry signal generated in a preceding sub-circuit of the first type. Since a multiplex switch operates faster than 3-bit or 4-bit wide carry look-ahead circuits, which operate in parallel in groups, the carry signals are consequently generated faster.

REFERENCES:
patent: 3100835 (1963-08-01), Bedrij
patent: 3316393 (1967-04-01), Ruthazer
patent: 3553446 (1971-01-01), Kruy
patent: 3906211 (1975-09-01), Glaser
patent: 4573137 (1986-02-01), Ohhashi
patent: 4675838 (1987-06-01), Mazin et al.
O. J. Bedrij, Carry-Select Adder, Jun. 1962, pp. 340 to 346.

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