Full adder circuit

Details Full adder circuit Full adder circuit

1997-10-16

1999-02-23

Moise, Emmanuel

Boots, shoes, and leggings

36478402, G06F 750

Patent

active

058751246

ABSTRACT:
A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A and B and carry in signal C and outputs sum signal S.sub.out. Carry signal calculation circuit 16 outputs carry out signal C.sub.out corresponding to the combination of the logic values of input signals A and B and carry in signal C. Sum signal calculation circuit (10) is composed of addition signal generation circuit (12) and sum signal generation circuit (14). Addition signal generation circuit 12 performs XOR logic operations on input signals A and B. Sum signal generation circuit 14 outputs the results of full addition operations on inputs signals A and B and carry in signal C as sum signal S.sub.out, based on the results of XOR logic operations by addition signal generation circuit (12) and carry in signal C.

REFERENCES:
patent: 3590230 (1971-06-01), Nordquist
patent: 4564921 (1986-01-01), Suganuma
patent: 4592007 (1986-05-01), Ohhashi
patent: 4601007 (1986-07-01), Uya et al.
patent: 4866658 (1989-09-01), Mazin et al.
patent: 4870609 (1989-09-01), Yasui et al.
patent: 5343418 (1994-08-01), Zinger

Affiliated with

Also associated with

Rating

Full adder circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Full adder circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Full adder circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-312680