Full adder

Details Full adder Full adder

1983-06-01

1986-01-14

Thomas, James D.

Boots, shoes, and leggings

307472, G05F 750

Patent

active

045649219

ABSTRACT:
A full adder is disclosed which comprises a first exclusive OR circuit for OR processing a first input signal and a second input signal, a second exclusive OR gate for OR processing an output signal of the first exclusive OR gate and a third input signal, and select circuit for selecting one of the first and second input signals and the third input signal according to a logical level of the output signal of the first exclusive OR gate. A sum signal of the first to third input signals, is obtained by the first exclusive OR means and the second exclusive OR means. The select means selects either the first or second input signal or the output signal of the third input signal according to a logical level of the output signal of the first exclusive OR means. The selected signal is used as a carry signal.

REFERENCES:
patent: 3766371 (1973-10-01), Suzuki
patent: 3767906 (1973-10-01), Pryor
patent: 4071905 (1978-01-01), Oguchi et al.
Japanese Patent Publication (KoKoKu) No. 49-34259 "Logical Circuit".
Ohwada et al., "LSI's for Digital Signal Processing," IEEE Journal of Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979.

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