Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-04-28
2001-11-20
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06320467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to transistor amplifiers and in particular to an F
t
doubler amplifier having a low-power biasing circuit.
2. Description of Related Art
Minority carrier charge storage in a bipolar transistor's base region causes it to behave electrically as a capacitor between its base and its emitter. This capacitance causes the transistor's current gain to decrease as the frequency of an input signal applied to its base increases.
The current gain of a transistor amplifier rolls off rapidly at higher input signal frequencies. The frequency at which the short circuit current gain of an amplifier falls to unity is commonly called the “current gain bandwidth” (F
t
) of the amplifier. It is used as a measure of the ability of an amplifier to provide a combination of bandwidth and current gain. Thus amplifier design is a tradeoff between gain and bandwidth, and an amplifier having a higher F
t
gives a circuit designer more flexibility when making that tradeoff.
FIG. 1
illustrates a well-known “F
t
doubler” amplifier
10
employing two identical differential amplifier stages
12
and
14
arranged to amplify an input current I
IN
to produce an output current I
OUT
with twice the F
t
of a single-stage amplifier. Thus for example, amplifier
10
could provide approximately twice the current gain at a given bandwidth or approximately twice the bandwidth for a given current gain.
Amplifier stage
12
includes two transistors Q
1
and Q
2
having emitters linked by a resistor R
1
and coupled to ground through biasing current sources I
1
and I
2
. Identical differential amplifier stage
14
includes two transistors Q
3
and Q
4
having emitters linked by a resistor R
2
and coupled to ground through biasing current sources I
3
and I
4
. Resistors R
7
and R
8
bias bases of transistors Q
1
and Q
4
, and bases of transistors Q
2
and Q
3
are interconnected. Amplifier stages
12
and
14
thus have inputs connected in series such that an input current signal I
IN
passes through both amplifier stage inputs. Thus each amplifier stage amplifies the same input current. The amplifier output differential currents I
OUT
appear at the interconnected collectors of transistors Q
1
and Q
3
and the interconnected collectors of transistors Q
2
and Q
4
. Since the outputs (transistor collectors) of the two stages connected in parallel, their output currents are summed to produce I
OUT
. Hence the current gain bandwidth of the two-stage amplifier
10
is twice that of an amplifier employing only a single stage.
When all transistors Q
1
-Q
4
are properly biased, each stage operates with maximum dynamic range. One practical difficulty in implementing the amplifier circuit of
FIG. 1
is in properly biasing the bases of transistors Q
2
and Q
3
to provide a bias voltage V
3
that is equal to the common mode average of voltages V
1
and V
2
at the bases of transistor Q
1
and Q
4
.
Some prior art F
t
doubler amplifier circuits use a simple voltage source
16
to bias the bases of transistors Q
2
and Q
3
to the correct bias voltage V
3
. To properly adjust the output voltage of source
16
it is necessary to accurately predict base voltages V
1
and V
2
, but it is often not easy to do that.
FIG. 2
illustrates a prior art F
t
doubler amplifier employing a biasing circuit
18
that senses V
1
and V
2
and automatically generates the correct bias voltage V
3
at the bases of transistors Q
2
and Q
3
. Bias circuit
18
includes two resistors R
3
and R
4
and a unity (voltage) gain feedback amplifier
20
. The matching resistors R
3
and R
4
connected in series between the bases of transistors Q
1
and Q
4
act as a voltage divider to produce the necessary bias voltage V
3
=(V
1
+V
2
)/2 at the bases of transistors Q
2
and Q
3
. The amplifier
20
isolates the bases of transistors Q
2
and Q
3
from resistors R
3
and R
4
. If amplifier
20
were omitted so that R
3
and R
4
were directly connected to the bases of Q
2
and Q
3
, the combined base bias current I
B
drawn by transistors Q
2
and Q
3
would be supplied through resistors R
3
and R
4
. This would increase the voltage drops across resistors R
3
and R
4
, thereby lowering the magnitude of V
3
below the desired level. Since amplifier
20
has a high input impedance, it can supply the necessary base current I
B
while drawing little current through resistors R
3
and R
4
, thereby maintaining V
3
at the proper biasing level. One drawback to amplifier
20
is that since it is a feedback amplifier driving a capacitive load, it may be subject to instability under some conditions.
Nonetheless, the two-stage “F
T
doubler” amplifier of
FIG. 2
is used in many applications. However it is not practical to expand the amplifier to include more than two stages so as to further multiply the F
T
of the amplifier. In the two-stage implementation illustrated in
FIG. 2
, the bias voltage V
3
is substantially constant because it is the average of opposing two ends of a differential signal. Hence unity gain amplifier
20
amplifies a DC signal. If we were to expand the two-stage amplifier to include more than two stages, then the bias voltages that a set of unity-gain amplifiers would have to supply to junctions between successive stages would have to oscillate with the same frequency as the input signal because they would not be the common mode average of two ends of a differential signal. Thus the unity gain amplifiers would have be able to operate at impractically high frequencies.
What is needed is a simple, low-power circuit for automatically biasing the bases of transistors in an F
T
multiplier amplifier that is stable under all conditions and which permits the amplifier to employ more than two stages.
SUMMARY OF THE INVENTION
An F
t
multiplier amplifier in accordance with the invention employs N similar differential amplifier stages having inputs connected in series so that each receives and amplifies the same input current. Stage output currents are summed to produce an amplifier output current so that the current gain of the amplifier is N times the current gain of each amplifier stage. Each amplifier stage includes a differential transistor pair, and adjacent stages are connected in series by interconnecting the base of one transistor of a stage to the base of another transistor of the adjacent stage at a circuit node.
For each circuit node at a junction between adjacent amplifier stages, the amplifier includes a corresponding bias circuit having a voltage divider for providing an appropriate bias voltage to the circuit node equal to the common mode average voltage at the bases of the other transistors of the two adjacent stages.
In accordance with the invention the bias circuit also includes a reference transistor linked to the corresponding node through a current mirror. The reference transistor is sized and biased relative to the amplifier stage transistors so that it draws a base current proportional to the base current drawn by the bases of amplifier stage transistors connected to the node corresponding to the biasing circuit. The current mirror amplifies the base current of the reference transistor with an appropriate gain to supply a bias current into the circuit node matching the base current drawn by the amplifier stage transistors.
The bias circuit is stable because it does not employ a feedback amplifier, and by using small reference transistor and a current mirror with high gain, the bias circuit consumes very little power.
It is accordingly an object of the invention to provide multistage F
T
multiplier amplifier.
It is another object of the invention to provide a stable, low-power, circuit for automatically biasing the interconnected bases of transistors of an F
T
multiplier amplifier.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method
Bedell David J.
Choe Henry
Credence Systems Corporation
Lee Benny
Smith-Hill and Bedell
LandOfFree
Ft multiplier amplifier with low-power biasing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ft multiplier amplifier with low-power biasing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ft multiplier amplifier with low-power biasing circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2579188