Front-surface N+ gettering techniques for reducing noise in inte

Details Front-surface N+ gettering techniques for reducing noise in inte Front-surface N+ gettering techniques for reducing noise in inte

1986-11-14

1989-01-03

Macon, Robert S.

Fishing, trapping, and vermin destroying

437 10, 437 12, H01L 2972

Patent

active

047960736

ABSTRACT:
Large "inactive" N+ regions are provided in P channel junction field effect transistors (JFETs) or NPN transistors immediately adjacent to "active" areas thereof to getter impurities away from the active areas. The ratio of inactive N+ area to the total area of the transistors is selected to provide suitably low noise measurements at low frequencies. Low noise amplifier circuitry is provided wherein all transistors in the AC signal path include unusually large ratios of inactive N+ area to total transistor area in order to provide greatly reduced low frequency noise levels.

REFERENCES:
patent: 3874936 (1975-04-01), d'Hervilly et al.
patent: 3929529 (1975-12-01), Poponiak
patent: 3933530 (1976-01-01), Mueller et al.
patent: 4053335 (1977-10-01), Hu
patent: 4061506 (1977-12-01), McElroy
patent: 4069068 (1978-01-01), Beyer et al.
patent: 4205332 (1980-05-01), Conti et al.
patent: 4371403 (1983-02-01), Ikubo et al.
"Gettering Technique", Barson et al., IBM Technical Disclosure Bulletin vol. 15, No. 6, Nov. 1972.
"Gettering Utilization Implant Damage and Highly Disordered Epitaxial Layer", Poponiak, et al., IBM Tech. Discl. Bulletin, vol. 19, No. 6.
"Ion-Implanted Gettering at Elevated Temperatures", Beyer et al. IBM Technical Discl. Bulletin, vol. 20, No. 8, Jan. 1978.
"Argon Implanation Gettering of Bipolar Devices", Poponiak et al., J. Electrochem Soc., Nov. 1977, pp. 1802-1805, vol. 124, No. 11.
"Gettering Technique & Structure", IBM Tech. Discl. Bulletin, vol. 16, No. 4, Bogardus et al.
"Gettering of Impurities by Intentional Double Diffusion", Leighton et al., IBM Technical Disclosure Bulletin, vol. 22, No. 8A, Jan. 1980.
"Self-Aligned Submicron Bipolar Transistor Process", Horng et al., IBM Technical Disclosure Bulletin, vol. 23, No. 7B, Dec. 1980.
"Process for Yield Improvement in Biopolar Devices", Barson et al. IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980.
"Simultaneous Formation of High Sheet Resistance Ion-Implanted--Resistors and Impurity Gettering for Bipolar Transistors", Putney IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978.
"Enhancement of Lateral P--N--P Current Gain by Gettering", Kesavan, et al., J. Electrochem. Soc. vol. 126, No. 4, pp. 642-644. Apr. 1979.
"Noise in Integrated Circuits", Chapter 11, pp. 607-636.
"Internal Gettering in Bipolar Process", Jastrzebski et al., J. Electrochem. Soc., Dec. 1984, pp. 2944-2953.
"Control of Stacking Fault Generation in Recessed Oxide Processing", Geipel, et al., IBM Technical Disclosure Bulletin vol. 21, No. 4, 9/78.

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