Frit-sealing process used in making displays

Details Frit-sealing process used in making displays Frit-sealing process used in making displays

1999-04-26

2002-03-12

Ramsey, Kenneth J. (Department: 2879)

Electric lamp or space discharge component or device manufacturi

Process

With assembly or disassembly

C445S043000

Reexamination Certificate

active

06354899

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to the field of fiber-based displays and methods of manufacture. More particularly, the invention pertains to fiber-based full-color plasma, plasma addressed liquid crystal, and field emission displays and their method of manufacture.
BACKGROUND OF THE INVENTION
All electronic display technologies are composed of a large array of display picture elements, called pixels arranged in a two-dimensional matrix. Color is added to these displays by subdividing each pixel element into three-color subpixels. The electronic display technologies can be further divided into a category known as flat-panel displays. The basic structure of a flat-panel display comprises two glass plates with a conductor pattern of electrodes on the inner surfaces of each plate with additional structure to separate the plates or create a channel. The conductors are configured in a x-y matrix with horizontal and vertical electrodes deposited at right angles from each other to allow for matrix addressing. Examples of flat-panel displays include plasma displays, plasma addressed liquid crystal (PALC) displays, field emission displays (FED), and the like.
Plasma display panels (PDP) have been around for about 30 years, however they have not seen widespread commercial use. The main reasons are the short lifetime, low efficiency, and cost of the color plasma displays. Most of the performance issues were solved with the invention of the three electrode surface discharge AC plasma display (G. W. Dick, “Three-Electrode per PEL AC Plasma Display Panel”, 1985 International Display Research Conf., pp. 45-50; U.S. Pat. Nos. 4,554,537, 4,728,864, 4,833,463, 5,086,297, 5,661,500, and 5,674,553). The new three electrode surface discharge structure advances many technical attributes of the display, but its complex manufacturing process and detailed structure makes manufacturing complicated and costly.
Currently, plasma display structures are built up layer by layer on specialty glass substrates using many complex processing steps.
FIG. 1
illustrates the basic structure of a surface discharge AC plasma display made using standard technology. The PDP can be broken down into two parts: top plate
10
and bottom plate
20
. The top plate
10
has rows of paired electrodes referred to as the sustain electrodes
11
a
,
11
b
. The sustain electrodes are composed of wide transparent indium tin oxide (ITO) electrodes
12
and narrow Cr/Cu/Cr bus electrodes
13
. These electrodes are formed using sputtering and multi-layer photolithography. The sustain electrodes
11
are covered with a thick (25 &mgr;m) dielectric layer
14
so that they are not exposed to the plasma. Silk-screening a high dielectric paste over the surface of the top plate and consolidating it in a high temperature process step forms this dielectric layer
14
. A magnesium oxide layer (MgO)
15
is deposited by electron-beam evaporation over the dielectric layer to enhance secondary emission of electrons and improve display efficiency. The bottom plate
20
has columns of address electrodes
21
formed by silk-screening silver paste and firing the paste in a high temperature process step. Barrier ribs
22
are then formed between the address electrodes
21
. These ribs
22
, typically 50 &mgr;m wide and 120 &mgr;m high, are formed using either a greater than ten layer multiple silk-screening process or a sandblasting process. In the sandblasting method, barrier rib paste is blade coated on the glass substrate. A photoresist film laminated on the paste is patterned by photolithography. The rib structure is formed by sandblasting the rib paste between the exposed pattern, followed by removal of the photoresist layer and a high temperature consolidation of the barrier rib
22
. Alternating red
23
R, green
23
G, and blue
23
B phosphors are silk-screened into the channels between the barrier ribs to provide color for the display. After silk-screening the phosphors
23
, the bottom plate is sandblasted to remove excess phosphor in the channels. The top and bottom plates are frit sealed together and the panel is evacuated and backfilled with a gas mixture containing xenon.
The basic operation of the display requires a plasma discharge where the ionized xenon generates ultraviolet (UV) radiation. This UV light is absorbed by the phosphor and converted into visible light. To address a pixel in the display, an AC voltage is applied across the sustain electrodes
11
which is large enough to sustain a plasma, but not large enough to ignite one. A plasma is a lot like a transistor, as the voltage is increased nothing happens until a specific voltage is reached where it turns on. Then an additional short voltage pulse is applied to the address electrode
21
, which adds to the sustain voltage and ignites the plasma by adding to the total local electric field, thereby breaking down the gas into a plasma. Once the plasma is formed, electrons are pulled out of the plasma and deposited on the MgO layer
15
. These electrons are used to ignite the plasma in the next phase of the AC sustain electrodes. To turn the pixel off, an opposite voltage must be applied to the address electrode
21
to drain the electrons from the MgO layer
15
, thereby leaving no priming charge to ignite the plasma in the next AC voltage cycle on the sustain electrodes. Using these priming electrons, each pixel can be systematically turned on or off. To achieve gray levels in a plasma display, each video frame is divided into 8 bits (256 levels) and, depending on the specific gray level, the pixels are turned on during these times.
There are presently three address modes of operation for a standard AC plasma display: (1) erase address (U.S. Pat. No. 5,446,344), (2) write address (U.S. Pat. No. 5,661,500), and (3) ramped voltage address (U.S. Pat. No. 5,745,086). The prior art wave forms for the matrix erase address waveform is shown in FIG.
2
. In the initial address cycle CA in the line display period T a discharge sustain pulse PS is applied to the display electrode
11
a
and simultaneously a writing pulse in applied to the display electrode
11
b
. In
FIG. 2
, the inclined line in the discharge sustain pulse PS indicates that it is selectively applied to lines. By this operation, all surface discharge cells are made to be in a written state.
After the discharge sustain pulses PS are alternately applied to the display electrodes
11
a
and
11
b
to stabilize the written states, and at an end stage of the address cycle CA, an erase pulse PD is applied to the display electrode
11
b
and a surface discharge occurs.
The erase pulse PD is short in pulse width, 1 &mgr;s to 2 &mgr;s. As a result, wall charges on a line as a unit are lost by the discharge caused by the erase pulse PD. However, by taking a timing with the erase pulse PD, a positive electric field control pulse PA having a wave height Va is applied to address electrodes
21
corresponding to unit luminescent pixel elements to be illuminated in the line.
In the unit luminescent pixel elements where the electric field control pulse PA is applied, the electric field due to the erase pulse PD is neutralized so that the surface discharge for erase is prevented and the wall charges necessary for display remain. More specifically, addressing is performed by a selective erase in which the written states of the surface discharge cells to be illuminated are kept.
In the display period CH following the address cycle CA, the discharge sustain pulse PS is alternately applied to the display electrodes
11
a
and
11
b
to illuminate the phosphor layers
23
. The display of an image is established by repeating the above operation for all line display periods.
The prior art waveforms for the matrix write address waveform is shown in FIG.
3
. At the initial stage of the address cycle CA, a writing pulse PW is applied to the display electrode
11
a
at the same time a sustain pulse is applied to display electrode
11
b
so as to make the potential thereof large enough to place each pixel element in the line in a

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