Frequency walled phase lock loop

Details Frequency walled phase lock loop Frequency walled phase lock loop

1993-09-17

1995-06-06

Chin, Stephen

Pulse or digital communications

Receivers

Angle modulation

331 17, 455260, H04L 27152, H03L 7107

Patent

active

054229111

ABSTRACT:
A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).

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