Electric power conversion systems – Frequency conversion without intermediate conversion to d.c.
Reexamination Certificate
2001-07-09
2004-09-28
Patel, Rajnikant B. (Department: 2838)
Electric power conversion systems
Frequency conversion without intermediate conversion to d.c.
C363S059000, C327S103000, C327S375000
Reexamination Certificate
active
06798678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency voltage converter, and particularly to a frequency voltage converter capable of holding linearity with respect to a modulated wave signal in a wide frequency band.
2. Description of the Prior Art
FIG. 9
is a circuit diagram showing a configuration of a conventional frequency voltage converter employed in a demodulator circuit as to frequency modulating methods such as FM, FSK, GFSK, etc. In
FIG. 9
, reference numeral
101
indicates a mixer circuit for converting a modulated wave signal Vin having an intermediate frequency to a frequency voltage, reference numeral
102
indicates a first input terminal of the mixer circuit
101
, reference numeral
103
indicates a second input terminal of the mixer circuit
102
, reference numeral
104
indicates a first capacitor (capacitance C
1
) connected to a signal line which branches off toward the second input terminal
103
, reference numeral
105
indicates a voltage source, reference numeral
106
indicates a second capacitor (capacitance C
2
), reference numeral
107
indicates an inductor (inductance L), and reference numeral
108
indicates a resistor (resistance value R), respectively. Further, Vout indicates a signal outputted from the mixer circuit
101
.
The operation of the frequency voltage converter will be next described.
When the modulated wave signal Vin is inputted, the relationship between a DC output obtained by removing the harmonics of the output signal Vout, and the modulated wave signal Vin is represented by the following equation (1):
V
in(
S
)/
V
out(
S
)∝
s
2
LC
2
/s
2
L
(
C
1
+C
2
)+
sL/R
+1,(
s=j
&ohgr;) (1)
When the variables in equation (1) are defined as in the following equation (2), the equation (1) is converted to the following equation (3).
&ohgr;
0
=1/{square root over (
L
(
C
1
+C
2
))},
Q=R/&ohgr;
0
L
(2)
V
out/
V
in&agr;&pgr;/2−tan
−1
[Q
(&ohgr;/&ohgr;
0−&ohgr;
0
/&ohgr;)] (3)
&ohgr;−&ohgr;
0
<<&ohgr;
0
/Q
(4)
As is derived from the above equation (3), the voltage of the output signal Vout results in one given as the function of a frequency &ohgr;. Under the condition in equation (4) above, the relationship between a DC output of the output signal Vout and the frequency of the input signal Vin approaches a proportionality relation. The center frequency of the input signal Vin is matched with &ohgr;
0
to thereby effect frequency voltage conversion on the input signal Vin.
The conventional frequency voltage converter is accompanied by a problem that since it is configured as described above, a Q value unavoidably results in a large value to maintain input amplitude at the second input terminal
103
where the center frequency &ohgr;
0
is low with respect to a frequency deviation (&ohgr;−&ohgr;
0
), and hence the value of (&ohgr;
0
/Q) becomes small, thereby incurring a difficult execution of frequency voltage conversion with holding linearity with respect to the frequency of the input signal Vin.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described drawback. It is therefor an object to provide a frequency voltage converter capable of holding linearity with respect to the frequency of an input signal over a wide frequency band and thereby carrying out frequency voltage conversion.
According to a first aspect of the present invention, there is provided a frequency voltage converter comprising: a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal; a second transmission line comprised of the other signal line which branches off from the input signal transmitting signal line; a mixer circuit having a first input terminal connected to the first transmission line and a second input terminal connected to the second transmission line; a delay-amount variable first delay line circuit placed in the second transmission line between a portion where the first transmission line and the second transmission line branch off from each other and the second input terminal of the mixer circuit; a third transmission line comprised of one signal line which branches off from a signal line for transmitting a reference signal having a predetermined frequency; a fourth transmission line comprised of the other signal line which branches off from the reference signal transmitting signal line; a delay-amount variable second delay line circuit placed in the fourth transmission line between a portion where the third transmission line and the fourth transmission line branch off from each other and a portion where the third transmission line and the fourth transmission line are joined to each other; and delay amount control means connected to the third transmission line, the fourth transmission line, a control section of the first delay line circuit and a control section of the second delay line circuit and for outputting the same control signal to the control section of the second delay line circuit and the control section of the first delay line circuit so that the reference signal passing through the fourth transmission line is delayed by a predetermined cycle with respect to the reference signal passing through the third transmission line.
Here, the first delay line circuit may comprise a plurality of stages of unit delay circuits, the second delay line circuit comprises a plurality of stages of unit delay circuits, and the unit delay circuits constituting the first delay line circuit and the unit delay circuits constituting the second delay line circuit respectively have the same circuit configuration.
In addition, when the number of stage of the unit delay circuits series-connected in the first delay line circuit, the number of stage of the unit delay circuits series-connected in the second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of stage for the first delay line circuit and the second delay line circuit may be respectively set so that a/b=fr/4fc is established, and the frequency of the reference signal may also be adjusted.
On the other hand, when the number of stages of the unit delay circuits series-connected in the first delay line circuit, the number of stages of the unit delay circuits series-connected in the second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of the stages for the first delay line circuit and the second delay line circuit may be respectively set so that a/b=fr/2fc is established, and the frequency of the reference signal may also be adjusted.
Further, the frequency voltage converter may include: a first buffer and a second buffer disposed in order from the side close to the branch portion between the branch portion and the first input terminal of the mixer circuit in the first transmission line, a third buffer disposed between the branch portion and the first delay line circuit in the second transmission line, a fourth buffer disposed between the first delay line circuit and the second input terminal of the mixer circuit in the second transmission line, a fifth buffer and a sixth buffer disposed in order from the side close to the branch portion between the branch portion and the joined portion in the third transmission line, a seventh buffer disposed between the branch portion and the second delay line circuit in the fourth transmission line, and an eighth buffer disposed between the second delay line circuit and the joined portion in the fourth transmission line, wherein the first buffer, the third buffer, the fifth buffer and the seventh buffer respectively have the same circuit configuration as an output buffer of the each unit delay circuit, and the second buffer, th
Komurasaki Hiroshi
Miki Takahiro
Sato Hisayasu
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Patel Rajnikant B.
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