Frequency-voltage conversion circuit and receiving apparatus

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Converting input frequency to output current or voltage

Reexamination Certificate

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C327S336000

Reexamination Certificate

active

06433591

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a frequency-voltage conversion circuit and a receiving apparatus applicable for a direct conversion receiver which receives and demodulates a FSK Frequency Shift Keying) signal.
A superheterodyne method and a direct conversion method are generally used in a FSK (Frequency Shift Keying) receiver. In each method, demodulation is carried out by the use of the known F-V (Frequency-Voltage) conversion.
Referring to
FIG. 1
, description will be made about a related direct conversion receiver using the F-V conversion.
In a Weber receiver illustrated in
FIG. 1
the direct conversion receiver, a base-band cross signal is brought up to intermediate frequency (namely, up-conversion is conducted), and the F-V conversion is performed.
The FSK signal sent from a receiver (not shown) is received by an antenna
101
, is amplified by a high frequency amplifier
102
, and is given to mixers
103
and
104
, respectively.
A local oscillator
107
produces an oscillation signal. The oscillation signal is shifted with &pgr;/2 by the use of a &pgr;/2 shifter
105
, and is given to the mixer
103
. Further, the frequency signal from the local oscillator
107
is directly given to the mixer
104
.
Low pass filters (hereinafter, abbreviated as LPFs)
106
and
108
are connected to the mixers
103
and
104
, respectively. In this condition, output signals from the mixers
103
and
104
are given to the LPSs
106
and
108
, respectively.
Each of the LPFs
106
and
108
has passing band equivalent to the base band signal, and realizes or obtains selectivity between adjacent channels. Further, the LPFs
106
and
108
supply output signals corresponding to signals from the mixers
103
and
104
into an up-conversion portion
130
.
In this case, the up-conversion portion
130
is composed of mixers
109
and
110
, a local oscillator
113
, a &pgr;/2 shifter, and an adder
112
, as illustrated in FIG.
1
.
With this structure, the mixer
109
is given with an oscillation signal from the local oscillator
113
. Further, the oscillation signal from the local oscillator
113
is shifted with &pgr;/2 by a &pgr;/2 shifter
111
, and is given to the mixer
110
.
Signals multiplied by the mixers
109
and
110
are added by the adder
112
Alternatively, the multiplied signals may be subtracted by a subtracter (not shown). An output signal of the adder
112
is converted by the use of a delay detection portion
114
.
In the above-mentioned Weber receiver
131
, a carrier wave frequency of the received FSK signal is defined as &ohgr;/2 &pgr; while frequency deviation is defined as ±&Dgr;&ohgr;/2 &pgr;. In this condition, the received FSK signal Sr
FSK
is represented by the following equation.
Sr
FSK
=cos(&ohgr;±&Dgr;&ohgr;)
t
In this event, when the output signal S
OSC1
of the local oscillator
107
is defined as S
OSC1
=sin &ohgr;t, the output signals S
MIX3
and S
MIX4
of the mixers
103
and
104
are represented by the following equations, respectively.
S
MIX3
=cos(&ohgr;±&Dgr;&ohgr;)
t
·cos &ohgr;
t =
½{cos(&ohgr;±&Dgr;&ohgr;+&ohgr;)
t
+cos(&ohgr;±&Dgr;&ohgr;·&ohgr;)
t}=
½{cos(2&ohgr;±&Dgr;&ohgr;)
t
+cos(±&Dgr;&ohgr;
t
)}
S
MIX4
=cos(&ohgr;±&Dgr;&ohgr;)
t
·sin &ohgr;
t =
½{sin(&ohgr;±&Dgr;&ohgr;+&ohgr;)
t
+sin(&ohgr;±&Dgr;&ohgr;·&ohgr;)
t}=
½{sin(2&ohgr;±&Dgr;&ohgr;)
t
+sin(±&Dgr;&ohgr;
t
)}
First terms of these equations are removed by the LPFs
106
and
108
. Therefore, the outputs S
LPF6
and S
LPF8
of the LPFs
106
and
108
are represented by the following equations.
S
LPF6
=½{cos(&Dgr;&ohgr;
t
)}  (1)
S
LPF8
=±½{sin(&Dgr;&ohgr;
t
)}  (2)
In this case, when calculation is carried out without limiter amplifiers
128
and
129
so as to be readily understood, an output signal Vout of the up-conversion portion
130
is modified as follows. Herein, it is to be noted that the output signal of the local oscillator
113
is defined by S
OSC2
=sin &ohgr;2t.
Vout=
½{cos(&Dgr;&ohgr;
t
)sin &ohgr;2
t
)}±½{sin(&Dgr;&ohgr;
t
)cos &ohgr;2
t
)}=½{sin(&ohgr;2±&Dgr;&ohgr;)}  (3)
From the above-mentioned result, the base band signal I, Q is converted to a signal having frequency deviation of ±&Dgr;&ohgr;/2&pgr;when the intermediate frequency &ohgr;2/2&pgr; is defined as a center.
Subsequently, when the limiter amplifiers
128
and
129
are inserted between the LPF
106
and the mixer
109
or between the LPF
108
and the mixer
110
, the condition is explained as follows.
When inputs into the mixers
109
and
110
becomes rectangular wave by the limiter amplifiers
128
and
129
, outputs S
LPF6′
and S
LPF8′
, are modified as follows by Fourier transforming the above-mentioned equations (1) and (2) Herein, it is to be noted that constant is defined as k=2/&pgr;.
S
LPF6′
=k
{cos(&Dgr;&ohgr;
t
)}+⅓·cos(3
&Dgr;&ohgr;t
) +⅕·cos(5
&Dgr;&ohgr;t
)+. . .}  (1′)
S
LPF8′
=k
{sin(&ohgr;2±&ohgr;)
t +
⅓·sin(3(&ohgr;2±&Dgr;&ohgr;)
t +
⅕·sin(5(&ohgr;2±&Dgr;&ohgr;)
t
)+. . .}  (2′)
Namely, the output Vout′ of the up-conversion portion
130
is similarly considered to be the modification of the above-mentioned equation (3). Thereby, the following equation is introduced.
Vout=
k
{sin(&ohgr;2±&ohgr;)
t +
⅓·sin(3(&ohgr;2±&Dgr;&ohgr;)
t +
⅕·sin(5(&ohgr;2±&Dgr;&ohgr;)
t
)+. . .}  (3′)
Consequently, it is found out that the conversion-up becomes possible even when the limiter amplifiers
128
and
129
are inserted between the LPF
106
and the mixer
109
or between the LPF
108
and the mixer
110
.
Although the Weber receiver
131
has been suggested as a SSB (Single Side Band) receiver, it is found out that the Weber receiver
131
is applicable as the FSK receiver, as explained above.
The output signal of the adder
112
is given to the delay detection portion
114
, and the F-V conversion is carried out in the delay detection portion
114
.
In
FIG. 2
, a detail structure of the delay detection portion
114
is illustrated. Further, a timing chart showing change (waveform) of each signal of each portion in the delay detection portion
114
is illustrated in FIG.
3
.
A signal V
A
from the adder
112
is converted into output signals V
B
and V
C
by removing amplitude demodulation components by the use of a limiter amplifier
119
.
Subsequently, the output signals V
B
and V
C
are converted into signals V
D
and V
E
having desired slopes at rising through common-emitter transistors
121
and
221
. Further, the signals V
D
and V
E
are converted into signals V
F
and V
G
by comparators
123
and
223
given with threshold level V
TH26
from a reference voltage
126
.
In this event, the transistors
121
and
221
are coupled to constant current sources
120
,
220
and capacitors
122
,
222
, respectively.
Moreover, the signals V
F
and V
G
are converted into a signal V
H
via an AND gate (namely logical product). Thereby, pulse signal line, which has constant amplitude and constant delay time &tgr;, is formed, as illustrated in FIG.
3
.
Finally, the pulse signal line V
H
is integrated by a LPF
125
, and converted into a voltage value V
I
corresponding to frequency. Further, the obtained voltage V
I
is converted into a logic data signal consisting of “1” and “0” by a converter (not shown).
In
FIG. 4
, frequency spectrums are illustrated so as to explain the above-mentioned structure. In an intermediate stage in the
FIG. 4
, center frequency between frequency of “1” and fr

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