Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation
Reexamination Certificate
2002-02-12
2004-05-18
Tran, Congvan (Department: 2681)
Telecommunications
Receiver or analog modulated signal frequency converter
Local control of receiver operation
15, 15, C375S316000, C375S327000
Reexamination Certificate
active
06738608
ABSTRACT:
BACKGROUND
1. Field
The present invention relates generally to data communication, and more specifically to a frequency-timing control loop for wireless (e.g., CDMA) communication systems.
2. Background
In a wireless communication system, an RF modulated signal transmitted from a source may reach a receiver at the destination, via a number of propagation paths (e.g., a line-of-sight path and/or reflected/scattered paths). In a multipath environment, the signal at a given receiver may thus include a number of instances of the transmitted signal. Each signal instance (or multipath component) may be associated with a different Doppler frequency shift due to movement of the receiver (or more precisely, due to relative motion between the receiver and the transmitter/reflector/scatterer associated with the signal instance). Each signal instance may further be associated with a different arrival time determined by the propagation path.
At the receiver, the received signal is conditioned and digitized to provide data samples. Conventionally, a rake receiver is used to process the data samples for multiple signal instances in the received signal. The rake receiver includes a number of finger processors, each of which may be assigned to process a respective signal instance based on the data samples. Each finger processor may include a rotator and an interpolator used to respectively provide frequency and time tracking for the assigned signal instance. In particular, the frequency error of the signal instance may be estimated with a frequency control loop and the rotator may then be used to remove this estimated frequency error from the data samples to provide frequency-translated data samples. Similarly, the timing error of the signal instance may be estimated with a timing control loop and the interpolator may then be used to re-sample the frequency-translated data samples at the optimal or near-optimal sample timing for the signal instance (i.e., the sample timing associated with the highest signal-to-interference-and-noise ratio (SINR) for the signal instance) to provide on-time samples. The on-time samples within each finger processor would then have the frequency and timing errors associated with the assigned signal instance removed.
The use of separate frequency and timing control loops to individually track the frequency and timing of a given signal instance provides good performance when the SINR of the received signal is low (such as for an IS-95 CDMA system). When such is the case, the SINR of the processed data samples (i.e., after rotation and interpolation) is not quite as sensitive to the rotation and interpolation of the data samples to remove the frequency and timing errors. However, for a system designed to operate at high SINRs (such as for an IS-856 CDMA system), the rotation and/or interpolation may result in noticeable degradation in the SINR of the processed data samples, which may then degrade performance.
There is therefore a need in the art for techniques to acquire and track the frequency and timing of a given signal instance, that are optimized for high SINR operating environments.
SUMMARY
Techniques are provided herein to acquire and track both the frequency and timing of a given signal instance such that re-sampling is not needed for the signal instance. This may then provide improved performance, especially at high SINR operating environments.
In an aspect, a frequency-timing control loop comprising a frequency control loop and a timing control loop is provided. The frequency control loop is used to acquire and track the frequency of a given signal instance (e.g., the strongest signal instance) in the received signal. The timing control loop is used to acquire and track the timing of the same signal instance and to adjust the phase of the ADC sampling clock so that the clock ticks are approximately aligned to the “optimum” sampling instants for the signal instance.
In a specific embodiment, the timing control loop includes a timing discriminator, a first loop filter, and a transfer gain element. The timing discriminator (which may be implemented as an early-late detector) processes data samples for the received signal to provide a timing error metric. The first loop filter then filters the timing error metric (e.g., based on a second-order loop filter). In an embodiment, the transfer gain element applies a non-linear function to the first loop filter output to provide a first control (a phase adjustment term) indicative of the timing error in the data samples for this given signal instance.
In a specific embodiment, the frequency control loop includes a frequency discriminator and a second loop filter. The frequency discriminator derives a second control (a frequency error metric) indicative of the frequency error in the data samples for the signal instance. The second loop filter then filters both the first and second controls (e.g., based on a first-order loop filter) to provide a third control. This third control may be used to adjust (1) the frequency of a local oscillator (LO) signal used to downconvert the received signal from RF to baseband, and (2) the phase of a clock signal used to digitize the downconverted signal to provide the data samples. In a typical implementation, the clock signal is derived by dividing down the LO signal, in which case alternatives (1) and (2) are equivalent.
Various aspects and embodiments of the invention are described in further detail below. The invention further provides control loops, methods, program codes, digital signal processors (DSPs), receiver units, terminals, base stations, systems, and other apparatuses and elements that implement various aspects, embodiments, and features of the invention, as described in further detail below.
REFERENCES:
patent: 5642243 (1997-06-01), Bliss
patent: 5778032 (1998-07-01), Tanaka et al.
patent: 5909148 (1999-06-01), Tanaka
patent: 5910945 (1999-06-01), Garrison et al.
patent: 5991349 (1999-11-01), Chen
patent: 6304619 (2001-10-01), Citta et al.
patent: 6560298 (2003-05-01), Froehling et al.
patent: 6563862 (2003-05-01), Knutson et al.
patent: 2001/0017902 (2001-08-01), Yamagata et al.
patent: 2002/0150190 (2002-10-01), Parr et al.
patent: 2003/0058952 (2003-03-01), Webster et al.
patent: 2003/0147426 (2003-08-01), Cronin et al.
patent: 818904 (1998-01-01), None
patent: 1024624 (2000-08-01), None
patent: 1154596 (2001-11-01), None
Black Peter J.
Sindhushayana Nagabhushana T.
Baker Kent D.
Qualcomm Incorporated
Tran Congvan
Wadsworth Philip
LandOfFree
Frequency-timing control loop for wireless communication... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency-timing control loop for wireless communication..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency-timing control loop for wireless communication... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3195937