Frequency synthesizing phase lock loop with unvarying loop param

Details Frequency synthesizing phase lock loop with unvarying loop param Frequency synthesizing phase lock loop with unvarying loop param

1993-04-27

1994-08-16

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 17, 331 25, H03L 7089, H03L 7107, H03L 718

Patent

active

053390504

ABSTRACT:
A PLL frequency synthesizer utilizes circuitry for altering pump current magnitude based upon division factors in the PLL. In one embodiment, pump current magnitude is responsive to the feedback division factor path, providing a constant gain over a wide frequency range, thereby providing a constant natural frequency and damping. In another embodiment, pump current magnitude is controlled as a function of both feedback and feedforward division factors, thereby maintaining a constant natural frequency with respect to the output frequency. In another embodiment, the output frequency is proportional to the VCO control signal raised to a power, with charge pump current controlled as a function of the feedforward division factor thus providing a natural frequency and damping factor which is constant with respect to output frequency. In another embodiment, gain control is provided as a function of at least one division factor in a PLL loop which does not utilize a charge pump. In one embodiment, a gain control circuit provides a gain control signal to at least one of a phase comparator and the variable frequency oscillator. In another embodiment, a gain control circuit provides a gain control signal to at least one adjustable gain stage.

REFERENCES:
patent: 4568888 (1986-02-01), Kimura et al.
patent: 4743867 (1988-05-01), Smith
patent: 4980653 (1990-12-01), Shepherd
patent: 4987387 (1991-01-01), Kennedy et al.
patent: 5128632 (1992-07-01), Erhart et al.

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