Frequency synthesizing circuit using a phase-locked loop

Details Frequency synthesizing circuit using a phase-locked loop Frequency synthesizing circuit using a phase-locked loop

1997-09-10

1999-03-30

Mis, David

Modulators

Frequency shift keying modulator or minimum shift keying...

332101, 375296, 375303, 375306, H03C 300, H04L 2712

Patent

active

058894438

ABSTRACT:
A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.

REFERENCES:
patent: 4937537 (1990-06-01), Nyqvist
patent: 5079520 (1992-01-01), Rapeli
patent: 5153468 (1992-10-01), Jokinen et al.
patent: 5175510 (1992-12-01), Satomaki
patent: 5311152 (1994-05-01), Lautzenhiser
patent: 5315183 (1994-05-01), Ruotsalainen
patent: 5317283 (1994-05-01), Korhonen
patent: 5325075 (1994-06-01), Rapeli

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