Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular frequency control means
Reexamination Certificate
2001-11-30
2004-05-11
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular frequency control means
C331S1170FE, C375S376000
Reexamination Certificate
active
06734741
ABSTRACT:
STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to communications circuits and, more particularly, to frequency synthesizers and PLL loops with digitally controlled oscillators.
2. Description of the Related Art
A great reduction of the transistor features in recently developed deep-submicron CMOS processes shifts the design paradigm towards more digitally-intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of a number of devices used but rather in terms of the occupied silicon area, no matter what the actual circuit complexity.
Analog and RF (radio frequency) circuits used in communication circuits, however, are not easily implemented in a deep-submicron CMOS process. For example, in Texas Instruments'CMOS process (C035) of 0.08 &mgr;m L-effective features a digital gate density of 150K equivalent (2-input NAND) gates per mm
2
. An average-size inductor for an integrated LC oscillator occupies about 0.5 mm
2
of silicon area. A low-noise charge pump, or a low-distortion image-reject modulator, both good examples of classical RF transceiver components, occupy roughly about the same area, which could be traded for tens of thousands of digital gates.
Migrating to a digitally-intensive synthesizer architecture brings forth the following well-known advantages: (1) fast design turn-around cycle using automated CAD tools (VHDL or Verilog hardware-level description language, synthesis, auto-place and auto-route with timing-driven algorithms, parasitic backannotation and postlayout optimization), (2) much lower parameter variability than with analog circuits, (3) ease of testability, (4) lower silicon area and dissipated power that gets better with each CMOS technology advancement (also called a “process node”) and (5) excellent chances of first-time silicon success. Commercial analog circuits usually require several design iterations to meet marketing requirements.
There is a wide array of opportunities that integration presents. The most straightforward way would be to merge various digital sections into a single silicon die, such as DRAM or Flash memory embedded into DSP or controller. More difficult would be integrating the analog baseband with the digital baseband. Care must be taken here to avoid coupling of digital noise into the high-precision analog section. In addition, the low amount of voltage headroom challenges one to find new circuit and architecture solutions. Integrating the analog baseband into RF transceiver section presents a different set of challenges: The conventional Bi-CMOS RF process is tuned for high-speed operation with a number of available passive components and does not fundamentally stress high precision.
Sensible integration of diverse sections results in a number of advantages: (1) lower total silicon area. In a deep-submicron CMOS design, the silicon area is often bond-pad limited; consequently, it is beneficial to merge various functions on a single silicon die to maximize the core to bond-pad ratio, (2) lower component count and thus lower packaging cost, (3) power reduction—no need to drive large external inter-chip connections and (4) lower printed-circuit board (PCB) area, thus saving the precious “real estate.”
Deep-submicron CMOS processes present new integration opportunities on one hand, but make it extremely difficult to implement traditional analog circuits, on the other. A digitally controlled oscillator (DCO) is very desirable, but it is important that the DCO be able to accurately track channels and modulate signals on a par with analog voltage controlled oscillators.
Therefore, a need has arisen for a method and apparatus for a high performance digitally controlled oscillator.
BRIEF SUMMARY OF THE INVENTION
In a first aspect of the present invention, a frequency synthesizer comprises a digitally controlled oscillator, including a plurality of switched capacitors, and control circuitry for selectively enabling and disabling the capacitors responsive to an oscillator tuning word. The control circuitry includes select circuitry for enabling a number of capacitors responsive to the oscillator tuning word and circuitry for dynamically varying which capacitors are enabled for a given oscillator tuning word to reduce non-linearities caused by slight variances in capacitive values.
This aspect of the invention provides the advantage that non-linearities due to slight variations in capacitive values in the digitally controlled oscillator are smoothed out over time.
In a second aspect of the present invention, a frequency synthesizer comprises a digitally controlled oscillator, including a plurality of switched capacitors, and control circuitry for selectively enabling and disabling the capacitors. The control circuitry includes circuitry for tuning the digitally controlled oscillator to a selected frequency by enabling and disabling capacitors in a first set and circuitry for modulating the digitally controlled oscillator by enabling and disabling capacitors mainly in a second set.
This aspect of the invention provides the advantage that a preferred range of capacitors can be used for modulation and drift corrections.
In a third aspect of the present invention, a frequency synthesizer comprises a digitally controlled oscillator, including a first set of switched capacitors and a second set of switched capacitors, where the second set of switched capacitors are in a physically separate area from the first set of switched capacitors, and control circuitry for selectively enabling and disabling the capacitors responsive to an oscillator tuning word. The control circuitry comprises first tracking circuitry for enabling and disabling capacitors responsive to an first portion of the oscillator tuning word and a first clock and second tracking circuitry for enabling and disabling capacitors responsive to a second portion of the oscillator tuning word and a second clock, wherein the second clock is significantly faster than the first clock.
This aspect of the invention provides the advantage that corrections associated with a rapidly changing part of a correction signal can be made with a physically separate set of capacitors, without contaminating the capacitors used for corrections responsive to a slower changing portion of the error signal.
REFERENCES:
patent: 4965531 (1990-10-01), Riley
patent: 5446420 (1995-08-01), Westwick
patent: 6028488 (2000-02-01), Landman et al.
patent: 6094105 (2000-07-01), Williamson
Radke, A 14-Bit Current-Mode Sigma-Delta DAC Based Upon Rotated Data Weighting, IEEE Journeal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, US.
Hung Chih-Ming
Leipold Dirk
Muhammad Khurram
Staszewski Robert B.
Brady III Wade James
Chang Joseph
Neerings Ronald O.
Pascal Robert
Telecky , Jr. Frederick J.
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