Frequency synthesizer with digital frequency lock loop

Details Frequency synthesizer with digital frequency lock loop Frequency synthesizer with digital frequency lock loop

2000-04-26

2001-07-31

Mis, David (Department: 2817)

Modulators

Frequency modulator

C332S127000, C332S128000, C327S156000, C331S014000, C331S016000, C331S017000, C331S023000, C375S376000, C455S260000

Reexamination Certificate

active

06268780

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency synthesizers for digital communication systems, and in particular, to frequency synthesizers using digital frequency lock loops and allowing direct modulation of the oscillator signal source.
2. Description of the Related Art
Time division multiple access (TDMA) wireless communication systems use discreet time slots for transmitting data at various defined frequencies. These data transmission time slots are separated by guard time slots to prevent signal collisions and allow the various signal sources within the system to settle at the defined transmission frequencies. Examples of such systems include wireless local area network (LAN) systems and cordless telephone systems, such as that defined according to the DECT standard. By way of example, the DECT time slot is approximately 400 microseconds, with a guard time slot of approximately 20-30 microseconds. Therefore, to achieve zero blindslot operation with a single signal source, a lock time of 20 microseconds is required.
One technique which has been used to implement a frequency synthesizer with a fast lock time is to replace a traditional phase lock loop (PLL) within the frequency synthesizer by a frequency counter, a digital-to-analog converter (DAC) and a signal processor (e.g., a microprocessor). The oscillator output is counted by the frequency counter to produce frequency count data. This frequency count data is processed by the signal processor to produce frequency control data which is converted to the appropriate analog signal by the DAC which drives the oscillator. One could also use a digital band select stage within the signal source (e.g., voltage-controlled oscillator) along with a lower resolution tuning DAC. One example of such an implementation can be found in U.S. Pat. No. 5,182,528, the disclosure of which is incorporated herein by reference. As noted, the DAC drives the oscillator and the frequency counter verifies the resulting frequency by counting the number of oscillator signal cycles within a predefined time period. From this count, the frequency can be derived. Accordingly, the locking time is defined by the settling time of the DAC. Some form of data storage circuit is used to store the DAC input data needed for the oscillator (e.g., a voltage-controlled oscillator) to generate the desired frequencies used for the system.
With the frequency counter connected directly to the output of the oscillator to count the cycles of the output signal, the counter will be driven by a continuous, or CW, signal during the receive mode of operation, but will be driven by a modulated signal during the transmit mode of operation. As noted, the frequency counter counts the number of oscillator signal periods that occur within a predefined time period which is derived from a system timing unit such as a crystal-referenced oscillator circuit. If the frequency is not within the desired frequency limits, the data presented to the DAC will be modified accordingly (via the data storage circuit) to compensate for any frequency differences until the next time the frequency is to be used. In the receive mode, with the signal having a constant frequency, this frequency compensation is easily done. However, in the transmit mode, with the output signal being modulated in frequency, the derived frequency count information provided by the counter will not accurately reflect the nominal, or center, frequency required to be generated by the oscillator circuit.
Accordingly, it would be desirable to have a way to monitor and maintain frequency lock for a frequency modulated signal while still providing for a fast frequency lock time by using a counter circuit in the feedback loop and a DAC to drive the oscillator circuit directly.


REFERENCES:
patent: 4533880 (1985-08-01), Geurts
patent: 5027087 (1991-06-01), Rottinghaus
patent: 5053723 (1991-10-01), Schemmel
patent: 5079526 (1992-01-01), Heck
patent: 5182528 (1993-01-01), Zuta
patent: 5216374 (1993-06-01), George et al.
patent: 5408687 (1995-04-01), Ooga
patent: 5412338 (1995-05-01), Richards et al.
patent: 5414390 (1995-05-01), Kovacs et al.
patent: 5430660 (1995-07-01), Lueker et al.
patent: 5430764 (1995-07-01), Chren, Jr.
patent: 5440259 (1995-08-01), Yokomura
patent: 5471661 (1995-11-01), Atkinson
patent: 5477194 (1995-12-01), Nagakura
patent: 5483203 (1996-01-01), Rottinghaus
patent: 5487093 (1996-01-01), Adresen et al.
patent: 5502420 (1996-03-01), Barclay
patent: 5506584 (1996-04-01), Boles
patent: 5521556 (1996-05-01), O'Shaughnessy et al.
patent: 5533059 (1996-07-01), Tsuda
patent: 5546433 (1996-08-01), Tran et al.
patent: 5552748 (1996-09-01), O'Shaughnessy
patent: 5568512 (1996-10-01), Rotzoll
patent: 5619535 (1997-04-01), Alvarez, Jr.
patent: 5642385 (1997-06-01), Alberty
patent: 5644601 (1997-07-01), Kawaguchi
patent: 5705955 (1998-01-01), Freeburg et al.
patent: 6081163 (2000-06-01), Ujiie et al.

Affiliated with

Also associated with

Rating

Frequency synthesizer with digital frequency lock loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Frequency synthesizer with digital frequency lock loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency synthesizer with digital frequency lock loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2462331