Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Utility Patent
1998-10-13
2001-01-02
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C327S536000, C327S156000, C327S157000
Utility Patent
active
06169457
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the technical field of frequency synthesizers. In particular, the invention pertains to a technology for ripple component compensation when the counter frequency division value is changed periodically.
BACKGROUND OF THE INVENTION
The cellular phone is of the frequency multi-channel access type. In order to shift the application frequency to an empty channel when the phone shifts from the standby to conversation mode, it is necessary to have a frequency synthesizer which can lock on an available channel at high speed.
In
FIG. 6
,
101
represents an example of the frequency synthesizer of the prior art using the PLL circuit technology of the fractional frequency division method. It is arranged inside the semiconductor device that forms a transceiver of the cellular phone.
This frequency synthesizer
101
contains the following parts: oscillator
131
, frequency divider
132
, reference clock signal generator
133
, phase comparator
134
, charge pump circuit
135
, and low-pass filter
136
. Said oscillator
131
has a configuration that outputs external signal OUT to the other circuit in the semiconductor device having frequency divider
132
and frequency synthesizer
101
.
Frequency divider
132
divides input external output signal OUT and generates a comparative signal. A comparative signal from frequency divider
132
and a reference clock signal output from reference clock generator
133
are input to phase comparator
134
; the phase of the signals is read. The result is used as a control signal which is output through charge pump circuit
135
and low-pass filter
136
to oscillator
131
.
For oscillator
131
, based on the input control signal, the frequency of external output signal OUT is changed such that the comparative signal and the reference clock signal are in phase. As a result, the frequency of external output signal OUT becomes a value equal to the frequency of the reference clock signal times the division value of frequency divider
132
.
However, with the cellular phone, where high frequencies of 800 MHz, 1 GHz, etc. are used as the reference, the inter-channel distance is 25 kHz, 12.5 kHz, etc. Consequently, it is necessary to form external output signal OUT with narrow channel intervals, such as 800.025 MHz, 800.050 MHz, etc.
On the other hand, in order to increase the response speed, the reference clock signal must be a high frequency signal. Consequently, the frequency division value of frequency divider
132
is changed periodically, an average frequency division value having a fraction value is generated, and the high-frequency reference clock signal is multiplied by the average frequency division value, so that external output signal OUT having the desired frequency is obtained.
For example, when a reference clock signal with a frequency of 200 kHz is used, suppose that the frequency division value is 4,000 for a duration of seven periods (35 &mgr;sec) of the reference clock signal, and the frequency division value is 4,001 for the duration of one period (5 &mgr;sec), then the average frequency division value of the 8 periods becomes 4,000.125 (=4,000+⅛), and external output signal OUT has a frequency of
200 kHz×(4000+⅛)=800.025 MHz
that is, 800.025 MHz.
During the eight periods, suppose the frequency division value of two periods is 4,001, the average frequency division value becomes 4,000.25. Consequently, the frequency of external output signal OUT becomes 800.050 MHz. In this way, since the frequency division value is made to change periodically, it is possible to obtain external output signal OUT at the desired frequency from the reference clock signal at a relatively high frequency.
However, when the frequency division value is made to change periodically as described above, even after external output signal OUT is locked to the desired frequency, the phase of the comparative signal and the phase of the reference clock signal are still not in agreement with each other. Consequently, from phase comparator
134
, a control signal indicating the phase difference between the comparative signal and the reference clock signal becomes a ripple current and is output through a charge pump circuit.
In
FIG. 7
, (a) represents the waveform of the comparative signal output from frequency divider
132
in the case of frequency division of external output signal OUT to frequency division value N and frequency division value N+1. (b) represents the reference clock signal. Since it is not in agreement with the phase of comparative signal (a), ripple current c is superimposed-on the control signal output from charge pump circuit
135
.
Such ripple current c not only degrades the receiving characteristics of the cellular phone or other communication device, but also acts as an interference component in transmission. Consequently, it becomes a serious problem.
Certain measures have been adopted to solve such problems in the prior art. For example, compensation circuit
140
made up of a charge pump circuit is arranged in frequency synthesizer
102
shown in FIG.
8
. As shown by (d) in
FIG. 7
, compensation current having a polarity opposite to ripple current c is generated, ripple current c is cancelled by compensation current d, and the phase of external output signal OUT is locked. In this state, the signal that changes the frequency of external output signal OUT is not input to oscillator
131
.
In order to cancel ripple current c by compensation current d, it is necessary to cancel the charge fed by ripple current c correctly by means of the charge supplied by compensation current d.
However, since the response of compensation circuit
140
, made up of a charge pump, is poor, compensation current d is output with a certain delay with respect to ripple current c. Also, the output time of compensation current d becomes longer than the output time of ripple current c. This is a disadvantage. For example, while the duration of output of ripple current c is as short as several hundred psec, the duration of compensation time d is several hundred nsec. Consequently, when ripple current c has a current value of a few mA, in order to provide the same charge amount but with opposite polarity, the current value of compensation current d becomes as small as a few &mgr;A, and it is impossible to perform the cancellation correctly. Consequently, it is difficult to eliminate the influence of ripple current c on conventional compensation circuit
140
.
FIG. 9
is a graph illustrating the relationship between the frequency component and optical intensity of output signal OUT of said frequency synthesizer
102
. The abscissa represents intensity, and the ordinate frequency. In this example, the reference clock signal has a frequency of 240 kHz, and the average frequency division value is 4,000+⅛. Around the center at the frequency (960.030 MHz) obtained by muultiplying the frequency of the reference clock signal with the average frequency division value, a spurious component is observed at a prescribed frequency interval. Such spurious components cause deterioration in the transceiving characteristics, and it is preferred that such spurious components be eliminated.
The purpose of the invention is to solve the aforementioned problems of the conventional technology by providing a type of frequency synthesizer which has no spurious components in the output signal, and which has excellent characteristics.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, the invention described in claim
1
provides a type of frequency synthesizer that contains an oscillator which outputs an output signal to the outside, a frequency divider which divides the external output signal output from the aforementioned oscillator so that its frequency division value is in periodic variation to generate a comparative signal, a phase comparator which compares the phase of the aforementioned comparative signal with the phase of a reference clock signal, and controls the a
Kinkead Arnold
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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