Frequency synthesizer with a plurality of frequency locking...

Details Frequency synthesizer with a plurality of frequency locking... Frequency synthesizer with a plurality of frequency locking...

2007-06-27

2009-08-18

Barnie, Rexford N (Department: 2819)

Oscillators

Plural oscillators

Selectively connected to common output or oscillator...

C331S056000, C327S298000, C327S156000

Reexamination Certificate

active

07576618

ABSTRACT:
The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, for controlling the frequency locking circuits. The control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. A related method for frequency synthesizing is also disclosed.

REFERENCES:
patent: 6463013 (2002-10-01), Liu
patent: 6741109 (2004-05-01), Huang et al.
patent: 2002/0001359 (2002-01-01), Skierszkan et al.
patent: 2003/0030475 (2003-02-01), Ishikawa
patent: 2005/0062505 (2005-03-01), Takahashi
patent: 2005/0138444 (2005-06-01), Gaskins
patent: 2006/0066376 (2006-03-01), Narendra et al.
patent: 2008/0079501 (2008-04-01), Hulfachor et al.
patent: 460769 (2001-10-01), None
Geum-Young Tak, et al., “A 6.3-9-GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications”, IEEE Journal of Solid-State Circuits, vol. 40, No. 8, Aug. 2005, pp. 1671-1679.

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