Frequency synthesizer with a phase-locked loop with multiple...

Details Frequency synthesizer with a phase-locked loop with multiple... Frequency synthesizer with a phase-locked loop with multiple...

1991-07-02

2001-02-20

Issing, Gregory C. (Department: 3662)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000

Reexamination Certificate

active

06191657

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer with a phase-locked loop with multiple fractional division.
A frequency synthesizer with a phase-locked loop comprises conventionally in the manner described, for example, in the book of U. L. Rhode entitled “Digital PLL frequency Synthesizers—Theory and Design”, 1983, Prentice Hall Inc. Englewoods Cliffs, a voltage-controlled oscillator, a variable-modulo divider, a phase detector, clock providing a reference frequency F
ref
, and possibly a loop filter. When the loop is locked, if M denotes the value set for the divider, the output frequency F
vco
from the voltage-controlled oscillator is equal to M times the value of the reference frequency F
ref
. When the value M set for the divider changes, the synthesized frequencies obtained change by steps equal to the reference frequency F
ref
, within the operating limits of the voltage-controlled oscillator.
To obtain a frequency synthesis step lower than F
ref
, it is known to introduce a fractional division loop which produces a frequency increment equal to a/Q times the reference frequency F
ref
, where Q is equal to the quotient of the reference frequency by the desired frequency step, where 0≦a≦Q−1.
Through a digital phase accumulator system, the main division ratio M is incremented by one unit for every occurrence of Q cycles of the reference frequency. The frequency step is then equal to the reference frequency divided by Q.
The advantage of this approach is that for comparable characteristics, the number of steps M to be set for the divider is reduced and that the loop filter has a higher cutoff frequency, which improves the response of the loop.
However, while the foregoing device is well suited to frequency synthesis, it is not appropriate for the synthesizers modulated in frequency or in phase from a modulation introduced, for example, in the reference frequency, for it appears that the maximum rate of this modulation is limited to low values. In addition, the synthesis frequency lines which appear at the output of the voltage-controlled oscillator and which are mainly due to the phase jitter of the phase comparator have relatively high levels which give to these synthesizers a relatively poor spectral purity.
However, when using not a single fractional division structure, but two of them, as is described in the French patent application NO 2 426 358 entitled “Synthétiseur de fréquence à division directe à pas après virgule”, it is possible to improve in a very significant manner the spectral purity of the signals from the synthesizers with fractional division.
However, for some applications, this improvement is not sufficient, in particular it does not allow to use such synthesizers in communications systems with fast frequency agility.
SUMMARY OF THE INVENTION
A purpose of the present invention is to remedy the above-mentioned disadvantages.
To this end, an object of the present invention is a frequency synthesizer with a phase-locked loop with multiple fractional division of the type comprising a single phase-locked loop controlled by a reference clock and comprised of a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter, characterized in that it also comprises a predetermined number n of fractional division structures, each implementing a frequency step P
i
×F
ref
lower than the reference frequency F
ref
, and in that each fractional division strucre is coupled in parallel with the programmable divider to add to the division rank M fractional increments P
i
such that the ratio between the frequency F
vco
provided by the voltage-controlled oscillator and the reference frequency F
ref
be defined as a function of the increments P
i
by the relationship :
F
vco
=
(
M
+
∑
1
n
⁢
P
i
)
⁢
F
ref
.


REFERENCES:
patent: 4573176 (1986-02-01), Yeager
patent: 4918403 (1990-04-01), Martin
patent: 5070310 (1991-12-01), Hietala et al.
patent: 5122767 (1992-06-01), Molina

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