Frequency synthesizer which suppresses a spurious

Details Frequency synthesizer which suppresses a spurious Frequency synthesizer which suppresses a spurious

1997-01-09

1998-09-01

Nelms, David C.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 18, 331 25, 331 46, 331 49, 331 51, H03L 700, H03B 2700

Patent

active

058015892

ABSTRACT:
A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.

REFERENCES:
patent: 4965553 (1990-10-01), Gilmore
patent: 5184093 (1993-02-01), Itoh et al.
patent: 5270669 (1993-12-01), Jokura
patent: 5497128 (1996-03-01), Sasaki
A. Bramble, Proc. 35th Ann.Freg.Control Symposium, pp. 406-414.

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