Frequency synthesizer using PLL architecture for wireless...

Details Frequency synthesizer using PLL architecture for wireless... Frequency synthesizer using PLL architecture for wireless...

2008-03-11

2008-03-11

Trinh, Sonny (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S260000, C455S196100

Reexamination Certificate

active

11060324

ABSTRACT:
An apparatus method to provide a frequency synthesizer using a phase locked loop in a communication device to provide a particular frequency allocation to generate an output from the PLL. The synthesizer includes a phase locked loop (PLL) circuit that has a feedback loop. The feedback loop has a feedback divider circuit that provides an N integer division of an output signal from the PLL in the feedback loop to close loop with the reference signal at a front end of the PLL. A value for feedback factor N to be used in the N integer division is based on a particular channel frequency selected and in which the feedback factor N is selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.

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