Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synthesizer
Reexamination Certificate
1996-09-25
2002-07-09
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synthesizer
C327S113000, C455S076000
Reexamination Certificate
active
06417703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency synthesizers. More particularly, the present invention relates to synthesizers configured to provide a high frequency output, such as from 600-1200 MHz, while supporting a high output resolution, such as 0.1 Hz, and a low settling time, such as 72 &mgr;sec or less.
2. Description of the Related Art
I. FIXED R SYNTHESIZER
FIG. 1
shows traditional components for a “fixed R” frequency synthesizer used as a component in a synthesizer operating from 600-1200 MHz and providing a 0.1 Hz resolution with a 72 &mgr;sec settling time. As shown, the fixed R frequency synthesizer of
FIG. 1
includes a reference oscillator
100
providing a signal having a frequency F
R
. A frequency divider
102
divides the output from reference oscillator
100
by a fixed amount R to provide a first input to a phase detector
104
. A voltage controlled oscillator (VCO)
106
provides the synthesizer output having a frequency Fo. A frequency divider
108
divides the frequency Fo of the VCO
106
by N to provide a second input to phase detector
104
. The output of the phase detector
104
is provided through an integrator
110
to the voltage control input of VCO
106
.
In operation, the value for R remains fixed, while N is incrementally changed to control the frequency Fo. The frequency (Fp) of signals provided at inputs of phase detector
104
remain constant. Thus, Fp=F
R
/R=Fo/N, and Fo is obtained as Fo=F
R
N/R. Resolution (RES) is then obtained by taking the difference in frequencies of the output signal Fo as N in frequency divider
108
is incrementally changed or RES=F
R
(N+1)/R−F
R
N/R=F
R
/R. Settling time (t
settle
) is determined in terms of the frequency Fp of signals provided to phase detector
104
as follows: t
settle
=4.5/(2&pgr;(Fp/10)).
Table A shows values for Fo, N and R in the circuit of
FIG. 1
with F
R
=10 MHz, a resolution of 1 KHz and a desired Fo=10.245 MHz±10 KHz. Note with RES=F
R
/R, R is 10,000. Further, Fp=F
R
/R=1 KHz making t
settle
=4.5/(2&pgr;(Fp/10))=7.2 msec.
TABLE A
Fo MHz
N
R
10.235
10235
10000
10.236
10236
10000
10.237
10237
10000
10.238
10238
10000
10.239
10239
10000
10.240
10240
10000
10.241
10241
10000
10.242
10242
10000
10.243
10243
10000
10.244
10244
10000
10.245
10245
10000
10.246
10246
10000
10.247
10247
10000
10.248
10248
10000
10.249
10249
10000
10.250
10250
10000
10.251
10251
10000
10.252
10252
10000
10.253
10253
10000
10.254
10254
10000
10.255
10255
10000
Utilizing the circuit of
FIG. 1
with a higher frequency output signal Fo, such as 600 MHz, to obtain a high resolution the settling time will be very large. For instance, if a desired RES=Fp=1 Hz, settling time t
settle
will be 7 seconds.
II. DIVIDE SUM SYNTHESIZER
To obtain a smaller settling time while maintaining a high resolution, a plurality of the fixed R synthesizers as shown in
FIG. 1
can be combined to form a “divide sum” synthesizer as shown in
FIGS. 2A and 2B
.
FIG. 2A
shows a fine resolution portion of a divide sum synthesizer, while
FIG. 2B
shows a coarse resolution portion of the divide sum synthesizer. The divide sum synthesizer of
FIGS. 2A-2B
can support a 600-1200 MHz output while providing a 0.1 Hz resolution and 72 &mgr;sec settling time.
The fine resolution portion of the divide sum synthesizer shown in
FIG. 2A
includes fixed R synthesizers
201
-
203
. The fixed R synthesizers
201
-
203
utilize a common reference oscillator
205
providing a signal having a frequency F
R
. The common reference oscillator
205
, such as a 10 MHz source shown, can be provided from a standard external signal source enabling the output of the divide sum synthesizer to be synchronized, or coherent with the common reference output F
R
.
The output of the fixed R synthesizer
201
(F
2
) is provided to a first input of a mixer
206
, while a second input of the mixer
206
is provided from an output (F
1
) of a VCO
208
. The output of VCO
208
is further provided through a frequency divider
210
which provides the output (F
A
) for the circuitry of FIG.
2
A. The frequency divider
210
divides the output of VCO
208
by a fixed number, shown here as 1000. The output of mixer
206
provides a signal (F
3
) through band pass filter (B.P.F.)
212
having a frequency equal to the difference in the signals F
1
and F
2
to an input of additional mixer
214
.
The output of the fixed R synthesizer
202
is provided through a frequency divider
216
to provide a signal (F
4
) to a second input of mixer
214
. Frequency divider
216
divides the output of fixed R synthesizer
216
by a fixed number, shown here as 5. The output of mixer
214
provides a signal (F
5
) through band pass filter
218
having a frequency equal to the difference in the signals F
3
and F
4
to an input of a phase detector
220
.
The output of the fixed R synthesizer
203
is provided through a frequency divider
222
to provide a signal (F
6
) to a second input of phase detector
220
. Frequency divider
222
divides the output of fixed R synthesizer by a fixed number, shown here as 100. The output of the phase detector
220
is then coupled through an integrator
224
to the voltage control input of VCO
208
.
Because the output frequency of VCO
208
is divided down through two mixers
206
and
214
before being provided to phase detector
220
, a significant variation in the initial frequency of VCO
208
from a predicted value used to set the output frequencies of fixed R synthesizers
201
-
203
may prevent the circuitry of
FIG. 2A
from locking the output frequency of VCO
208
. To presteer the output frequency of VCO
208
to a desired initial frequency, and assure lock, a user controlled D/A converter
226
is provided. The D/A converter
226
has its output connected through summer
228
along with the output of integrator
224
to provide the voltage control input to VCO
208
.
In operation, the output frequency of each of the fixed R synthesizers
201
-
203
can be determined utilizing the equations provided with respect to
FIG. 1
as follows:
F
2
=
F
R
N
1
/
R
1
F
4
=
F
R
N
2
/(5
R
2
)
F
6
=
F
R
N
3
/(100
R
3
)
Using the equations for F
2
and F
4
, the frequencies of signals output from mixers
206
and
214
can be determined as follows:
F
3
=
F
2
−
F
1
=
F
R
N
1
/
R
1
−
F
1
F
5
=
F
3
−
F
4
=
F
R
(
N
1
/
R
1
−
N
2
/(5
R
2
))−
F
1
With the phase detector
220
assuring that the signals F
5
and F
6
are equal, the frequency of signal F
1
can be derived from the above equations for F
5
and F
6
as follows:
F1
=
F
R
(
N1
/
R1
-
N2
(
5
R2
)
)
-
F
R
N3
/
(
100
R3
)
=
F
R
(
N1
/
R1
-
N2
(
5
R2
)
-
N3
/
(
100
R3
)
)
Assuming that the values for R
1
, R
2
and R
3
are respectively 5, 50 and 100, and utilizing the fact that F
A
=F
1
/10000, the frequency F
A
can be derived as follows:
F
A
=200
N
1
−4
N
2
−
N
3
/10.
With values for R
1
, R
2
, R
3
, and F
R
chosen as shown in
FIG. 2A
, values for N
1
, N
2
and N
3
are shown in
FIG. 2A
selected to provide an output signal F
A
ranging from 100-200 KHz. For the values for N
1
, N
2
and N
3
shown, frequencies at the outputs of the oscillators and inputs to phase detectors are also shown.
With the value for N
1
being variable while N
2
and N
3
remain fixed, as shown in
FIG. 2A
, output resolution for the circuit of
FIG. 2A
, taking into account frequency divider
210
, is calculated as RES=F
R
/(10000R
1
)=200 Hz. Alternatively, with N
2
being variable, while N
1
and N
3
remain fixed, taking into account frequency divider
216
, output resolution will be RES=F
R
/(50000R
2
)=4 Hz. To provide an even greater resolution N
3
can be varied while N
1
and N
2
remain fixed, making the output resolution RES=F
R
/(100000R
3
)=0.1 Hz.
Anritsu Company
Fliesler Dubb Meyer & Lovejoy LLP
Le Dinh T.
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