Frequency synthesizer suited for use in a time division multiple

Details Frequency synthesizer suited for use in a time division multiple Frequency synthesizer suited for use in a time division multiple

1988-04-07

1989-07-04

Heyman, John S.

Multiplex communications

Wide area network

Packet switching

328 15, 370 70, H03B 1900, H04J 102

Patent

active

048454362

ABSTRACT:
A frequency synthesizer includes a 1/N divider for generating an address clock signal the frequency of which is 1/N times the frequency of an input signal, a memory for storing samples in a unit sine and cosine wave which is read out in response to the address clock signal to produce a frequency deviation signal, and a quadrant modulator responsive to both of the input signal and frequency deviation signal for producing an output signal the frequency of which is the difference between the input signal and frequency deviation signal. The frequency of the frequency deviation signal is varied by digitally changing N to modify the frequency of the output signal while maintaining the continuousness of the output signal phase.

REFERENCES:
patent: 4100498 (1978-07-01), Alsup et al.
patent: 4159526 (1979-06-01), Mosley, Jr. et al.
patent: 4297641 (1981-10-01), Sterzer
patent: 4437066 (1984-03-01), Gordon
patent: 4486846 (1984-12-01), McCallister et al.
"PCM Communication Technology", by N. Kaneko, SANPO Publication Inc., FIG. 5.24.

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