Frequency synthesizer having first phase locked loop frequency m

Details Frequency synthesizer having first phase locked loop frequency m Frequency synthesizer having first phase locked loop frequency m

1985-10-15

1987-06-16

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 22, 331 25, 331 31, H03L 718, H03L 722

Patent

active

046738916

ABSTRACT:
A Frequency synthesis stage comprises two phase locked loops. The first (O.sub.1, D.sub.1, M, CP.sub.1, D.sub.2) divides the frequency Fo+.DELTA. derived from preceding stages by N/Q, N being a variable integer, and adds to the result a standard frequency P which is in a fixed ratio with a value representative of large frequency steps so as to give an intermediate frequency F.sub.A, while the second (O.sub.2, M.sub.0, M.sub.1, CP.sub.2 D.sub.3) multiplies F.sub.A by NQ/r. P and Q are selected so that the product PQ is approximately equal to the mean of the limit values desired for the output frequency.

REFERENCES:
patent: 4225829 (1980-09-01), Kumagai
patent: 4458329 (1984-07-01), Remy

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