Frequency synthesizer architecture

Details Frequency synthesizer architecture Frequency synthesizer architecture

2007-11-20

2007-11-20

Lee, Benny (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C327S156000, C455S260000

Reexamination Certificate

active

11196492

ABSTRACT:
A frequency synthesizer is provided with a PLL, including a divider by N circuit and a phase generation circuit which is connected to the output of the VCO of the PLL. The phase generation circuit generates a predetermined number of phases synchronized on the frequency of the VCO and at intervals from each other equal to a time difference representative of a phase error measured by a phase comparator of the PLL. A signal generation circuit provides an intermediate signal starting from the phases, the period of which is dependent on the time difference and a first adjustment parameter. The intermediate signal is applied to the divider by N circuit. A correction circuit determines the phase error accumulated during N−1 periods of the intermediate signal and makes a correction of the intermediate signal every N periods of the intermediate signal as a function of the accumulated phase error such that the loop becomes stable.

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patent: WO 03/029002 (2003-05-01), None
Preliminary French Search Report, FR 0408737, dated Nov. 17, 2004.

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