Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-02-06
2004-01-20
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06681235
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-033493 filed Feb. 10, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer and a Gaussian noise generator. In particular, the present invention relates to a frequency synthesizer having a high frequency resolution in a wide bandwidth and a Gaussian noise generator using the same.
Conventionally, a DDS (direct digital synthesizer) is used as a frequency synthesizer capable of generating a periodic function signal with its stable frequency.
FIG. 14
is a block diagram depicting a configuration of this DDS
10
.
That is, in
FIG. 14
, in a waveform memory
11
, amplitude data on a periodic function (for example, sine wave function) is stored by one cycle in a storage region that can be specified by an address signal of L bits.
This waveform memory
11
sequentially outputs amplitude data stored in an address specified by the address signal.
In addition, frequency setting means sets frequency data A for specifying an address interval (phase interval) in which amplitude data is read out from the waveform memory
11
.
Further, an adder
13
adds the frequency data A set by the frequency setting means
12
and an output from a latch circuit
14
, and the addition result thereof is outputted to the latch circuit
14
.
This latch circuit
14
latches an output of the adder
13
every time the circuit receives a clock signal CK, and outputs this latch output as data for specifying a phase to the adder
13
and waveform memory
11
.
Furthermore, a D/A converter
15
converts amplitude data outputted from the waveform memory
11
into an analog signal, and outputs the converted analog signal.
In the thus configured DDS
10
, an address signal relevant to the waveform memory
11
increases with the intervals A like A,
2
A,
3
A, . . . in synchronism with the clock signal CK.
In this manner, from the waveform memory
11
, the amplitude data D (A), D (
2
A), D (
3
A), . . . corresponding to each address are read out sequentially.
The amplitude data D (A), D (
2
A), D (
3
A), . . . are converted into analog signals sequentially by means of the D/A converter
15
, and are continuously outputted as a periodic function signal.
Here, assuming that bit number M of frequency data A set by the frequency setting means
12
is equal to bit number L of an address signal, an output frequency F is obtained as fc A/2
L
. Thus, 2
L
−1 from fc·½
L
to fc·2
L-1
/2
L
frequencies can be generated.
However, in this system, there is a problem that the setting resolution of a frequency that can be outputted is limited by bit number L of an address of the waveform memory
11
.
Thus, in the DDS requiring a higher setting frequency, the frequency data A of M bits is composed of a L-bit integer portion and m-bit decimal number portion.
The adder
13
and the latch circuit
14
are configured so that L+m bit addition and latching are enabled, and upper L bits of an output of the L+m bits of the latch circuit
14
are outputted as an address signal to the waveform memory
11
.
In this manner, a signal can be generated at a frequency resolution that is not limited by address bit number L of the address memory
11
.
Using the above DDS
10
, for example, when an attempt is made to generate a signal of an arbitrary frequency by defining an output (for example, 100 MHz) of a hydrogen maser oscillator of 10
−15
in frequency precision as a reference clock signal CK, a frequency resolution of 16 digits or more is required for the DDS
10
.
In this case, log
2
10
16
is almost equal to 2
54
, and thus, it is required to use a binary adder of 54 bits as an adder
13
.
However, if adding process with such many bits is performed, there is a problem that a delay time caused by a carry propagation process of the adder
13
exceeds a cycle of the clock signal CK, whereby practical use is not obtained.
That is, when the carry propagation delay time per bit of the adder
13
is defined as Ta, the maximum delay time of the entire adder
13
is obtained as (L−1) Ta.
This maximum delay time is required to be within a time shorter than a cycle 1/fc of a clock signal.
Hence, in the current adder, such adding process with many bits cannot be performed at a clock frequency (100 MHz). Therefore, there is a problem that an upper limit of a frequency that can be generated is forced to be reduced by reducing the clock frequency.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problems. It is an object of the present invention to provide a frequency synthesizer capable of acquiring a high frequency resolution in a wide bandwidth and a Gaussian noise generator using the same.
In order to achieve the foregoing object, according to one aspect of the present invention, there is provided a frequency synthesizer comprising:
amplitude data output means for, when L-bit data is received, outputting amplitude data with a predetermined periodic function of a phase specified by the data;
frequency setting means for setting data of (K+L−1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal as frequency data;
a K-bit counter for counting the clock signal;
L-set product and sum computation circuits for subjecting frequency data of (K+L−1) bits from the frequency setting means into L-set K-bit data in which a start bit is shifted by one bit each other, and computing a logical product between a count output of K bits from the counter and a unit of bits, thereby obtaining a total number of bits in which the calculation result is 1 by each set; and
a shifting/adding circuit for adding each total number data obtained by the L-set product and sum computation circuits, by shifting bits, and outputting the least significant L bits of the addition result to the amplitude data output means.
In addition, in order to achieve the foregoing object, according to another aspect of the present invention, there is provided a frequency synthesizer, comprising:
amplitude data output means for, when L-bit data is received, outputting amplitude data with a predetermined periodic function of a phase specified by the data;
frequency setting means for setting data of (K+L−1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal as frequency data;
a K-bit counter for counting the clock signal;
L-set product and sum computation circuits for subjecting frequency data of (K+L−1) bits from the frequency setting means into L-set K-bit data in which a start bit is shifted by one bit each other, and computing a logical product between a count output of K bits from the counter and a unit of bits, thereby obtaining a total number of bits in which the calculation result is 1 by each set;
a shifting/adding circuit for adding each total number data obtained by the L-set product and sum computation circuits by shifting bits, and outputting the least significant L bits of the addition result to the amplitude data output means;
a latch circuit for latching L-bit data inputted to the amplitude data output means every time the latch circuit receives a latch signal;
an adding circuit for adding an output of the shifting/adding circuit and an output of the latch circuit, and outputting the least significant L bits of the addition result to the amplitude data output means; and
a control circuit for initializing the counter to a value 1 or a value close thereto every time frequency data set by the frequency setting means is changed, and outputting a latch signal to the latch circuit in accordance with a timing at which L-bit data corresponding to the initialized value is outputted from the shift adder, thereby substantially making continuous a phase value immediately before frequency change of amplitude data outputted from the
Ishibe Kazuhiko
Uchino Masaharu
Anritsu Corporation
Mai Tan V.
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