Frequency synthesizer

Details Frequency synthesizer Frequency synthesizer

2000-11-22

2003-09-16

Nguyen, Lee (Department: 2682)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S260000, C331S00100A, C331S017000

Reexamination Certificate

active

06622010

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a frequency synthesizer. More specifically, the present invention pertains to a frequency synthesizer that can accurately compensate for ripple current.
BACKGROUND OF THE INVENTION
For a cellular phone of the multi-channel access type, in order to shift the current frequency to a vacant channel, there must be a frequency synthesizer that allows high-speed lock-up.
In
FIG. 3
,
101
represents a conventional frequency synthesizer used in a fractional frequency division type PLL (Phase Locked Loop) circuit.
Said frequency synthesizer
101
is set inside a semiconductor integrated circuit that forms the transceiver of the cellular phone. It has the following parts: oscillator
131
, frequency divider
132
, reference clock signal generator
133
, phase comparator
134
, charge pump circuit
135
, low-pass filter
136
, compensation circuit
137
, and controller
138
. In said oscillator
131
, an external output signal OUT is generated at the prescribed frequency, and the external output signal OUT is output to frequency divider
132
and the other circuits in the semiconductor integrated circuit where said frequency synthesizer
101
is set.
Frequency divider
132
frequency divides the external output signal OUT that is input, and it generates a comparison signal that is output to phase comparator
134
. Said phase comparator
134
compares the phase of the comparison signal input from frequency divider
132
with the phase of the reference clock signal input from reference clock signal generator
133
, and outputs a signal corresponding to the phase difference to charge pump circuit
135
. Based on the signal corresponding to the input phase difference, charge pump circuit
135
creates a positive
egative output current flow and this output current is output as a control signal through low-pass filter
136
to oscillator
131
.
Based on the input control signal, oscillator
131
changes the frequency of external output signal OUT, and it operates such that the phase of the comparison signal comes into sync with the phase of the reference clock signal. As a result, the frequency of external output signal OUT is equal to the frequency of the reference clock signal times the frequency division value of frequency divider
132
.
Said frequency divider
132
is controlled by controller
138
, and the frequency division value is made to change periodically. As an example, when the frequency of the reference clock signal is 200 kHz, suppose the frequency division value is 5000 for the period of 7 cycles (35 &mgr;sec), and it is 5001 for the period of 1 cycle period (5 &mgr;sec). In this case, the average frequency division value for the 8 cycles is 5000.125(=5000+⅛), and the frequency of external output signal OUT is locked to 1000025 kHz, that is, the reference clock signal times the average frequency division value.
Suppose the frequency division value is 4000 for 6 cycles, and 4001 for 2 cycles during 8 cycles, the average frequency division value is 4000.25, and the frequency of external output signal OUT becomes 800.050 MHz.
In this way, when the average frequency division value has a value with precision to after the decimal point, it is possible to use high frequencies such as 800 MHz, 1 GHz, etc. with narrow channel intervals of 25 kHz, 12.5 kHz, etc.
However, when the frequency division value is changed periodically as aforementioned, even after the external output signal OUT is locked at the desired frequency, the phase of the comparison signal and the phase of the reference clock signal are not in sync, and there is a phase difference. Consequently, the control signal output from phase comparator
134
contains a ripple current.
In
FIG. 4
, a indicates the waveform of the comparison signal input from frequency divider
132
after external output signal OUT is locked as the frequency division value changes between N and N+1, b represents the waveform of the reference clock signal, and c represents the waveform of the ripple current in the control signal output from charge pump circuit
135
due to the fact that the phase of the comparison signal and the phase of the reference clock signal are not in sync.
The ripple current contained in the control signal generates spurious signals in the external output signal. This not only degrades the reception characteristics of cellular phones and other communications equipment, but it also becomes a component that degrades transmission. It is a serious problem.
In this frequency synthesizer
101
there is a compensating circuit
137
having a DA converter
141
and a capacitor
142
. DA converter
141
changes the voltage applied to capacitor
142
, and it generates a compensating current having the same charge quantity as the ripple current yet having an opposite sign. The compensating current is superimposed onto the control signal output from charge pump circuit
135
. The ripple current is cancelled out. As a result, an external output signal OUT having no spurious components is obtained.
The charge quantity of the ripple current that varies over time changes such that it becomes an integer times a prescribed theoretical unit charge quantity. The theoretical unit charge quantity indicates the product of the phase difference between the comparison signal and the reference clock signal and the output current of charge pump circuit
135
.
As an example, as aforementioned, when the frequency of external output signal OUT is 1000025 kHz, suppose the output current of charge pump circuit
135
is a constant current of +1 mA or −1 mA, the following Q
r
becomes the unit charge quantity:
Qr
=(⅛)×(1/1000025 kHz)×1 mA×½=62.5×10
−15
(Coulomb)  (101)
Then, ripple current is generated at the same period as that of the reference clock signal with charge quantities from ±1 up to ±7 times said unit charge quantity Q
r
(±7Q
r
) in the following order +7Q
r
→+5Q
r
→3Q
r
→1Q
r
→−1Q
r
→−3Q
r
→−5Q
r
→−7Q
r
.
In order to compensate for such ripple current, if the capacitance of capacitor
142
is C
1
, voltage V
e
from the following formula:
C
t
·V
e
=Q
r
  (102)
is used as a unit by DA converter
141
to convert voltage V
d
applied to capacitor
142
in the following magnitudes and order: −7V
e
, −5V
e
, −3V
e
, −1V
e
, +1V
e
, +3V
e
, +5V
e
, +7V
e
, which results in a compensating current having the same charge quantity as that of the ripple current but having an opposite sign. The compensating current is superimposed onto the output current of charge pump circuit
135
. In this way, the ripple current can be cancelled out.
As explained above, in said frequency synthesizer
101
, a compensating current is preset so that by superimposition, the ripple current can be compensated for correctly. However, when the ripple current that is actually output varies due to certain reasons, such as variation in the circuit constants of the circuit elements, etc., it is impossible to compensate for the ripple current accurately.
A general object of the present invention is to solve the aforementioned problems of the conventional methods by providing a device which can accurately compensate for the ripple current.
SUMMARY OF THE INVENTION
The object and other features of the invention are attained, in accordance with one aspect of the invention by a frequency synthesizer characterized by the fact that it has he following parts: an oscillator, wherein the frequency of the output oscillating signal controlled corresponding to a control signal; a frequency divider of the fractional frequency dividing type which frequency-divides the aforementioned oscillating signal and generates a comparison signal; a reference clock signal generator which generates a reference clock signal; a phase comparator which compares the phase of said comparison signal and the ph

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