Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-06-13
2001-12-11
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S160000, C331S00100A, C331S017000, C377S047000, C377S052000
Reexamination Certificate
active
06329855
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-167303, filed Jun. 14, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer of a pulse swallow method.
A PLL (Phase-Locked Loop) synthesizer of a pulse swallow method is known.
In the usual synthesizer, since all the circuits except the reference signal oscillator and the voltage controlled oscillator can be constructed with a digital circuit, the circuit has been miniaturized by integrating these circuits. In this specification, this is called “Synthesizer IC”, and, hereinafter, it is expressed as “PLLIC”.
When integrating the above-mentioned circuits, it is preferable to construct the circuit by C-MOS in view of the low consumption current. But, since it is difficult to directly divide a local frequency of the radio set, it is general that the first stage of frequency dividing section is assumed to be a circuit configuration such as ECL (Emitter-Coupled Logic) etc. which can operate at high speed though the consumption current somewhat increases.
In that case, when assuming the number of dividings of frequencydividers (called as a prescaler), which is constructed with ECL to be K and when inserting variable frequencydividers with the number of dividings N to it in series, and incrementing and decrementing N by one, the number of dividings in the whole can be changed only with intervals of K.
In the radio set, the communication frequency is provided with a constant interval (channel interval), and it is necessary to switch a reference signal according to it. Therefore, since the frequencies of signals of dividing compared with the above-mentioned reference signal with phase comparator
2
must coincide with 1/K of channel interval, the response of the entire circuit slows, and it is unsuitable to the high-speed channel switch required to the radio set of a digital method.
Therefore, variable frequencydividers of the number of dividings A are provided in the frequency section in parallel with a variable frequencydivider which divides N, and two numbers of dividings (K, K+1) are switched by prescaler
5
.
Such a circuit configuration is known as a pulse swallow method, and detailed operation will be described later. The number of dividings can be changed by one by such a circuit configuration.
By the way, when the miniaturization is required like the cellular phone, synthesizer ICs are integrated in addition to other circuits.
However, when integrating various circuits by integration, since PLLIC is a digital circuit, the dividing component and the harmonic component thereof are easily generated as a noise, especially, the influence on the circuit (for example, mixer and limiter, etc.), which treats the low level signal, becomes a disadvantage.
For example, a case that PLLIC is applied to the cellular phone, will be considered.
The frequency of the first intermediate frequency signal often used in the cellular phone is 130 MHz band. At this time, since it is necessary to adjust the reception frequency to ±130 MHz, the frequency of the first local signal is in the vicinity of 1 GHz.
Here, in the prescaler of PLLIC, in view of the easiness of the configuration, the values of the number of dividings K are often assumed to be n power of two. The output frequency of the prescaler becomes almost 31 MHz when assuming K=32, here.
Then, the fourth harmonic of the output frequency of the prescaler becomes 124 MHz, and is near the frequency of the first intermediate frequency signal. Since the communication channel is allocated in tens of MHz band, an actual cellular phone, the frequency of the first intermediate frequency signal is corresponding to the harmonic component of the prescaler output at a considerably high probability, and the number of channels before and after that will be influenced by the high frequency component.
In addition, since the frequency, to which the harmonic component corresponds, is quad-wave of output of the prescaler with 32 harmonics, and corresponds to eight dividings in the entire frequencydivider of PLLIC, the channel influenced by the harmonic component includes the point with the largest influence, and includes the number of channels before and behind that.
As mentioned above, it is preferable to integrate a part of the radio section by integration, and to miniaturize the circuit, but PLLIC, which is a digital circuit, has the problem that the obstruction might be given to other circuits, especially, the receiver circuit.
It is certain to separate PLLIC with the receiver circuit to solve this problem, but the request of the radio set to the miniaturization cannot be satisfied.
In another method, the number of dividings of prescaler is set to a frequency, which does not become a disadvantage, but this method also has the fault.
Even when limiting to the cellular phone, by considering use with other systems, since there is two kinds of use in which either of upper or lower frequency of the reception frequency is taken in the first local signals, it is difficult to achieve the configuration to which those frequencies are not surely corresponding. To solve the above-mentioned problem surely, since synthesizer IC, which sets PLLIC, must be manufactured, according to each system, furthermore, each upper and lower frequency of a local signal, and to each user according to circumstance, there is a disadvantage in a general purpose.
As described above, in the conventional frequency synthesizer, when integrating the synthesizer with the circuit of the receiver circuit of the radio set by integration, there is a disadvantage that there is fear to obstruct the circuit of the receiver circuit by the noise generated from the synthesizer part.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a frequency synthesizer, which does not obstruct circuit of receiver circuit without losing the versatility, even when integrating the synthesizer with circuit of receiver circuit by integration.
To achieve the above-mentioned object, a frequency synthesizer according to the present invention is characterized by comprising a voltage controlled oscillator to generate a oscillation signal of a frequency corresponding to a control voltage; a divider to divide the oscillation signal and to generate a dividing signal; a reference signal oscillator to generate a reference signal; a phase comparator to obtain a phase error between the reference signal and the dividing signal; and a filter to smooth the comparison result of the phase comparator and generate the control voltage, in which the divider comprises a swallow counter which times a switching time of a number of dividings, a prescaler to divide the oscillation signal by the number of dividings corresponding to the switching time timed with the swallow counter, a variable divider to divide a dividing result of the prescaler by a number of dividings set by a user, and a dividing number change controller to change a relation between the number of dividings and a switching time of the numbers of dividings in the prescaler.
The preferred manners of the above-mentioned frequency synthesizer are as follows.
(1) The swallow counter indicates a passage of the switching time of the number of dividings at a level of a signal, the prescaler divides the oscillation signal by the number of dividings corresponding to the signal level indicated by the swallow counter, and the dividing number change controller changes a polarity of a signal to the prescaler.
(2) A change in the relation in the dividing number change controller is performed based on a control signal obtained by a predetermined arithmetic.
(3) The prescaler selectively sets one of 2
n
and 2
n+1
to the number of dividings according to the switching time timed with the swallow counter, and the swallow counter times the switching time of the number of dividings of the presc
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Le Dinh T.
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