Frequency synthesis device

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synthesizer

Reexamination Certificate

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Details

C327S105000, C327S156000, C455S260000, C455S183100, C331S018000

Reexamination Certificate

active

06522177

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the field of frequency synthesis, and more particularly to frequency synthesis with high spectral purity.
2. Description of the Prior Art
It is recalled here that frequency synthesis is the technique of generating a signal oscillating at an adjustable frequency with high precision and high spectral purity. Frequency synthesis is very widely used in different areas of electronics, for example in radio and TV signal broadcast and reception, telecommunications, instrumentation, clock signal generation, etc.
At present, frequency synthesis is generally produced from one or several circuits known as phase locked loops (PLL). In this case, the synthesis is “indirect”, inasmuch as the signal produced at the output is generated by an oscillator different from the reference source.
A PLL circuit can produce at its output a signal which is variable by frequency jumps from a signal of fixed frequency, referred to as the reference frequency.
FIG. 1
is a diagram which shows schematically the main elements that form a classical PLL circuit. The above-mentioned reference frequency Fref is produced by an oscillator circuit
4
whose time base is generally a quartz crystal
6
. The signal at the frequency Fref is sent to a first comparison input C
1
of a phase comparator
8
via a divider
9
programmable for the reference frequency; the second comparison input C
2
of the phase comparator
8
receives the output signal from a voltage controlled oscillator (VCO)
12
after a frequency division by a factor N, as shall be explained further.
The programmable divider
9
allows to select the exact desired frequency at input C
1
of the phase comparator
8
as a function e.g. of the frequency plan established for the oscillating system into which the PLL circuit is integrated. Its function is to divide the frequency Fref at the input by a programmable factor R, where R is an integer or a fraction. The frequency at the output of the divider
9
is thus Fref/R.
The pulse-like signal at the output S of the phase comparator
8
, after integration by a low-pass filter
10
, appears in the form of a voltage whose magnitude is proportional to the phase difference between the signals applied at the first and second comparison inputs C
1
and C
2
.
The low-pass filter
10
serves to integrate the current or voltage fluctuations arising from the phase comparison performed by the comparator
8
, so that the oscillator
12
can correctly follow the evolutions of that signal while complying to the stability criteria according to the theory of feedback controlled systems.
The pulse-like voltage or current is first supplied to a low-pass filter
10
, and thereafter to the voltage-controlled oscillator
12
. The latter produces a signal whose frequency F
1
is proportional to this control voltage and which, in the circuit considered, also constitutes the output frequency F
1
of the PLL.
A feedback of this output signal from oscillator
12
to the phase comparator
8
passes through a frequency divider
14
, such that the signal supplied at the second comparison input C
2
of the comparator
8
has a frequency equal to F
1
/N at the feedback, where N is an integer or a fraction.
The phase comparator
8
thus produces at its output S a signal whose magnitude is proportional to the phase difference between this signal of frequency F
1
/N and the phase of the reference signal, possibly after a frequency division by the divider circuit
9
. It shall be understood that when N is varied by programming, the oscillator
12
shall see its frequency vary correspondingly up to the point where the two comparison signals are in phase.
When this condition is reached, the loop is in the stable mode and we have, at the level of the comparator, the identity F
1
/N=Fref/R. Thus, the frequency F
1
at the output is N/R times Fref. The PLL equation is stable for Fref/R=F
1
/N, whence an output frequency of: F
1
=(N/R)Fref.
By programming the values N and R, it is possible to obtain, from the reference signal of fixed frequency Fref, a range of frequencies of which each frequency is an integral or fractional multiple of that reference frequency. The reference frequency Fref therefore establishes the resolution in frequency variation, the latter only occurring in jumps of Fref or Fref(N/R).
There also exists another frequency synthesis technique which is known as direct digital synthesis (DDS). This approach consists in mathematically constructing, in an autonomous fashion, a signal having a desired waveform (generally sinusoidal) by directly calculating trigonometrical values for each phase angle increment of the signal considered. Such a circuit shall be briefly described with reference to FIG.
2
.
The calculation of these trigonometrical values is performed by a direct digital synthesis block formed by a trigonometrical calculation unit
22
. This unit operates in synchronous binary logic from a clock signal Sh supplied by an oscillator circuit
4
which can be of the same type as presented in the context of FIG.
1
. Each digital sample thus obtained is then transformed into a voltage value using a digital-to-analog converter
24
. The evolution of this voltage in concert with the execution of the successive calculations reproduces the desired waveform at the desired frequency Fsynth. Generally, each calculation of a trigonometric value for a given angle is performed in pace with a cycle of the clock Fh of the oscillator circuit
4
. Also, to obtain a signal having good resolution, it is necessary to dispose of a relatively dense number of calculation points for each cycle reproduced. According to the theory of sampled systems, the clock frequency Fh must be higher than the frequency of the reproduced signal Fdds, the optimization typically being obtained when the clock signal frequency is greater by a factor at least equal to three times that frequency.
Nowadays, with digital architectures becoming increasingly integrated, direct digital synthesis is technically and economically feasible, but it is implemented in conjunction with indirect synthesis to offer solutions that meet frequency synthesis requirements of the new telecommunications systems, which are always demanding as regards spectral quality and frequency resolution, as well as in precision and frequency stability.In this context, indirect synthesis uses frequency transposition architectures with interlocked PLLs in view of minimizing phase noise at the output. These loops are difficult to implement as regards both feedback stability criteria and spurious spectral spikes. Moreover, the practical aspects of their construction pose problems, especially as regards presetting the oscillators so as to be in the capture range. This problem is linked to the narrow bandwidth of beats at the outputs of mixers associated with the phase comparators. The beat frequencies used are moreover undesirable at the spectrum output. It is also necessary to manage an approach voltage for the output oscillator. Consequently, achieving a frequency synthesis calls for a compromise to be made between a high comparison frequency, a small increment resolution, a high frequency acquisition speed, and an adequate band coverage at the output, requiring the use of broadband oscillators. These problems of frequency synthesis shall now be described in the context of a concrete example based on a digital radio or TV transmitter in the UHF band. Efforts in this field are directed to digital modulation transmission systems for both television and radio. Compared to analog transmissions, digital technology allows a much denser occupation of the spectrum and a greater immunity to noise and interference problems. As regards radio frequency broadcasting, present day digital TV and radio broadcasting programs (also known as DAB or DVBT respectively for digital audio broadcasting and digital video broadcasting terrestrial) aim to exploit the UHF IV and V and VHF band III carrier frequency bands.
The modulatio

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