Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2001-07-31
2003-08-19
Tokar, Michael (Department: 2819)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S078000, C331S057000
Reexamination Certificate
active
06608529
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to frequency generation, synthesis, and processing. More particularly, the present invention relates to filters, oscillators, phase-locked loops (PLLs), and frequency synthesizers used to generate various operational frequencies for digital signal processing circuitry and communications equipment.
BACKGROUND INFORMATION
Modern communications equipment design relies on the generation of various periodic output frequencies. While oscillators are preferred for their overall stability and purity, individual oscillators differ, and the issues of amplitude stability and spectral purity are ever-present. Moreover, while stable oscillators built with high-Q crystals often exhibit excellent spectral purity, such oscillators can usually only be tuned over a range of several hundred parts per million. Since most communications equipment must operate at a number of different frequencies spanning a considerably larger range, and because it is usually not economical to fabricate separate oscillators for each frequency to be generated, frequency synthesizers are widely used in modern communications circuit design.
A frequency synthesizer typically makes use of a single quartz-controlled (i.e. crystal) reference oscillator combined with a phase-locked loop (PLL) and other circuit elements to provide a multitude of output frequencies traceable to the highly-stable reference. The ideal synthesizer then, can provide a wide operational frequency range using a single high stability oscillator.
More and more channels are required to support the public demand for instant contact with others as the use of personal communications devices becomes more popular. Those skilled in the art also know that the capability to effect multi-channel communications provides a robust and scalable mechanism for circuit designs to achieve the goal of effectively utilizing all available channels. Given their advantages, synthesizers are thus often used as the core of multi-channel communications circuit design. Designs are more robust when the ability exists to shut down a noisy channel and switch to another which is not affected by disturbances along the transmission path. Designs are scalable when individual functional blocks can be repeated within a circuit and used to occupy newly-available bandwidth, such as when a particular communications session ends. Other factors affecting the number of channels available include increasing data transmission rates, which typically serves to enlarge the number of channels and increase bandwidth availability. On the other hand, the occurrence of one or more notches within a band of frequencies or even within a single communications channel (perhaps caused by destructive interference, resonant inter-circuit connectors, etc.) reduces the availability of channels.
Thus, the ability to provide many channels for communication, along with full usage of individual channel capacity, is often a major goal for the communications circuit designer. However, the low-pass control loop filters used in PLL-based synthesizers often require a large resistance-capacitance (RC) time constant (which implies large values of resistance and capacitance) to provide proper control signals for the voltage-controlled oscillator (VCO) which is also part of the PLL circuit. These loop filters thus require large amounts of circuit surface area and power to operate.
Increasing data rates also raise other problems with conventional technology. While the relatively low data rates used in digital subscriber line (DSL) and orthogonal frequency division multiplexing (OFDM) applications allow data processing in the discrete time domain using conventional multi-purpose digital signal processor (DSP) and PLL integrated circuits, higher-speed communication, in the realm of 50 gigabits/second, is not possible with current DSP technology. Conventional discrete time domain-based design approaches do not lend themselves to high data rate communications. And, as mentioned above, circuit designers are also concerned with the amount of circuit real estate and power required by conventional PLL-based multi-frequency solutions.
Thus, there is a need in the art to increase the number of channels available for stable, low-jitter communication, along with reducing dependence on conventional DSP-based design. Such apparatus and methods should foster the use of high-speed circuitry, along with repeatable, low-power circuit modules for increased scalability, taking advantage of the integration and low-power requirements offered by complementary metal-oxide semiconductor (CMOS) and other circuit fabrication technologies.
REFERENCES:
patent: 4931748 (1990-06-01), McDermott et al.
patent: 5550515 (1996-08-01), Liang et al.
patent: 5572168 (1996-11-01), Kasturia
patent: 5692023 (1997-11-01), Clark
Mai Lam T
Schwegman Lundberg Woessner & Kluth P.A.
Tokar Michael
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