Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2002-05-24
2004-10-05
Callahan, Timothy P. (Department: 2816)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S17700V
Reexamination Certificate
active
06801093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for generating a clock synchronized with a reference clock by a PLL (Phase Locked Loop) method.
2. Description of the Prior Art
According to a conventional frequency synchronous method, degradation in the stability of a reference clock leads to degradation in the stability of the output frequency of a voltage-controlled oscillator (VCXO) following the reference clock. To solve this problem, there is provided an apparatus shown in FIG.
1
. In this apparatus, a synchronous clock
109
output from a voltage-controlled oscillator
5
is branched and divided by a frequency division circuit
7
. A frequency division circuit output
105
is compared with a reference clock
103
by a phase comparison circuit
4
. A frequency adjustment and calculation circuit
1
receives phase difference data
106
from the phase comparison circuit
4
, calculates such a control value as to eliminate the phase difference, and sends a control value
107
to a conversion circuit
3
. The conversion circuit
3
sends a control voltage
108
to the voltage-controlled oscillator
5
. Then, the voltage-controlled oscillator
5
outputs a synchronous clock
109
corresponding to the voltage. In this apparatus, a highly stable oscillator
52
is connected to the frequency adjustment and calculation circuit
1
. The highly stable oscillator
52
monitors the reference clock, and restricts the follow-up performance of the synchronous clock output from the frequency synchronous apparatus to the reference clock.
Japanese Unexamined Patent Publication No. 5-268078 discloses an arrangement which holds a voltage value obtained when the reference clock and VCO clock synchronize with each other, and if the frequency difference between the reference clock and VCO exceeds the pulling range, switches the current voltage to the held voltage value to achieve phase locking. This arrangement enables quick recovery of re-synchronization when the frequency steps out.
However, the former apparatus requires the highly stable oscillator
52
, which increases the circuit scale and cost. The latter apparatus is a means for re-synchronizing the synchronous clock with the reference clock when the synchronous clock changes. If the reference clock degrades, the current voltage is set to the held voltage value, and the voltage value of VCO is reset to a value used in synchronization. This inhibits a holdover state, and the frequency of the synchronous clock changes to a held frequency used in synchronization. That is, the synchronous clock disadvantageously coincides with the changed reference clock.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a frequency synchronous apparatus and method capable of outputting a stable synchronous clock even when the frequency of a reference clock varies and the characteristics of a voltage-controlled oscillator change over time.
To achieve the above object, according to the first aspect of the present invention, there is provided a frequency synchronous apparatus for outputting a synchronous clock synchronized with a reference clock, comprising a switch which selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal, a frequency division circuit which divides a frequency of the synchronous clock, a phase comparison circuit which detects a phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value, a frequency adjustment and calculation circuit which performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time, a memory which holds the synchronous control value output from the frequency adjustment and calculation circuit, a conversion circuit which converts the synchronous control value output from the frequency adjustment and calculation circuit into a control voltage value, and a voltage-controlled oscillator which outputs a synchronous clock on the basis of the control voltage value.
The memory in the first aspect holds a synchronous control value output from the frequency adjustment and calculation circuit when the highly stable clock is output in accordance with the mode switching signal, and two synchronous control values output from the frequency adjustment and calculation circuit when a frequency of the highly stable clock is set to a frequency higher by a predetermined value and to a frequency lower by the predetermined value.
To achieve the above object, according to the second aspect of the present invention, there is provided a frequency synchronous apparatus for outputting a synchronous clock synchronized with a reference clock, comprising a frequency division circuit which divides a frequency of the synchronous clock, a phase comparison circuit which detects a phase difference between an output clock from the frequency division circuit and a reference clock, and outputs a phase difference value, a frequency adjustment and calculation circuit which performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time, a memory which holds a predetermined synchronous control value output from the frequency adjustment and calculation circuit, a conversion circuit which converts the synchronous control value output from the frequency adjustment and calculation circuit into a control voltage value, and a voltage-controlled oscillator which outputs a synchronous clock on the basis of the control voltage value.
The memory in the second aspect holds a synchronous control value output from the frequency adjustment and calculation circuit when a highly stable clock is input to the phase comparison circuit instead of the reference clock, and two synchronous control values output from the frequency adjustment and calculation circuit when a frequency of the highly stable clock is set to a frequency higher by a predetermined value and to a frequency lower by the predetermined value.
To achieve the above object, according to the third aspect of the present invention, there is provided a frequency synchronous control method of controlling a voltage-controlled oscillator to output a synchronous clock synchronized with a reference clock, comprising the steps of detecting a phase difference between the synchronous clock and the reference clock, performing synchronous control so as to eliminate the phase difference, controlling the voltage-controlled oscillator on the basis of a synchronous control value at this time, and holding the synchronous control value in a memory.
In the frequency synchronous control method of the third aspect, a synchronous control value which adjusts a phase difference value between the synchronous clock and a highly stable clock instead of the reference clock to 0, and two synchronous control values output which adjust the phase difference value from the synchronous clock to 0 when a frequency of the highly stable clock is set to a frequency higher by a predetermined value and to a frequency lower by the predetermined value can be held in the memory in advance.
In the frequency synchronous control method of the third aspect, when synchronous control is so performed as to eliminate the phase difference between the synchronous clock and the reference clock, whether a synchronous control value which adjusts the phase difference value to 0 is a value falling within a control range whose upper and lower limit values are the two synchronous control values held in the memory in advance can be checked, if the synchronous control value is the value falling within the control range, synchronous control which adjusts the phase difference value to 0 can be performed, and if the synchronous control value is a value falling outside t
Callahan Timothy P.
Cox Cassandra
NEC Corporation
LandOfFree
Frequency synchronous apparatus and frequency synchronous... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency synchronous apparatus and frequency synchronous..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency synchronous apparatus and frequency synchronous... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3324341