Pulse or digital communications – Pulse code modulation – Differential
Reexamination Certificate
1999-03-05
2001-03-13
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Pulse code modulation
Differential
C341S143000
Reexamination Certificate
active
06201835
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to techniques for chopper-stabilizing a delta-sigma modulator to improve the conversion accuracy thereof, and more particularly to reducing conversion inaccuracies caused by intermodulation between chopper clock signals and the delta-sigma modulator output which causes high frequency “tones” to be aliased back to the base band of the delta-sigma modulator.
By way of background, the closest prior art is believed to include the combination of the assignee's U.S. Pat. No. 5,703,589 (Kalthoff et al.) issued Dec. 30, 1997, incorporated herein by reference and U.S. Pat. No. 5,115,202 (Brown) issued May 19, 1992. FIGS. 2A and 2B of U.S. Pat. No. 5,703,589 show a differential chopper-stabilized delta-sigma analog-to-digital converter. The first integrator of the delta-sigma modulator is shown in FIG. 2A of the '589 patent. The differential input signals to operational amplifier 18 are alternately reversed or swapped by fixed-frequency chopper signals &phgr;
CHA
and &phgr;
CHB
, which are shown in FIG. 3 of the '589 patent. Similarly, the differential output signals produced by operational amplifier 18 also are alternately swapped in response to the same fixed-frequency chopper clock signals. This known chopping technique shifts DC offset and low frequency noise signals to a higher frequency equal to or close to the fixed frequency of the chopper clock signals. Such shifted offset and noise signals then are filtered out by a digital filter circuit.
A shortcoming of the foregoing chopper stabilization technique is that there inevitably is parasitic coupling between the fixed-frequency chopper clock signal and the delta-sigma modulator output containing high frequency “tones” when the analog input is at certain DC levels. This parasitic coupling, also referred to as “intermodulation”, produces low frequency “images” of the high frequency tones within the base band of the delta-sigma modulator. The image signals within the base band cause conversion inaccuracy.
Note that even though one could choose a different chopping clock frequency, one will inevitably have a tone problem at certain input DC levels. This is because the frequency of a high frequency tone is a function of the DC level of the input signal level. When the high frequency tone moves close to the chopping frequency, intermodulation will bring the high frequency tone into the base band.
Above mentioned U.S. Pat. No. 5,115,202 discloses use of a pseudo-random frequency chopper clock generation circuit 12 that swaps the differential inputs and outputs of an operational amplifier, to thereby chopper stabilize the DC input offset and low frequency noise signals of the differential input signal. The pseudo-randomization of the chopper clock signal frequency effectively “spreads” chopper clock noise energy throughout the frequency spectrum, and thereby reduces the intermodulation between the amplifier input signal and the chopper clock signal which causes a side image of the input signal.
There remains an unmet need for a way of avoiding conversion errors caused in a delta-sigma analog-to-digital converter by intermodulation between a chopper stabilization clock signal and high frequency tones in the output of the delta-sigma modulator.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a technique for reducing conversion errors due to intermodulation in a delta-sigma analog-to-digital converter.
It is another object of the invention to reduce the sensitivity of analog-to-digital conversion to intermodulation in a delta-sigma analog-to-digital converter.
It is another object of the invention to provide a clock signal having frequency-shaped pseudo-random frequency spectrum.
It is another object of the invention to reduce the effects of offset and low frequency noise in a delta-sigma modulator or an amplifier.
Briefly described, and in accordance with one embodiment thereof, the invention provides a frequency-shaping pseudo-random clock signal generator circuit including a pseudo-random sequence generator and a digital delta-sigma modulator. The digital delta-sigma modulator includes a feedback delay circuit, a first digital adder receiving as inputs a pseudo-random sequence signal produced by the pseudo-random sequence generator and an error feedback signal produced by the feedback delay circuit. A 1-bit quantizer produces a frequency-shaped pseudo-random clock signal in response to the pseudo-random sequence signal and the error feedback signal, and a second digital adder produces a digital error signal as an input to the feedback delay circuit in response to the frequency-shaped pseudo-random clock signal and the error feedback signal.
In another embodiment, the sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation is reduced by applying a pseudo-random sequence signal to a first input of a first adder, and applying an error feedback signal to a second input of the first adder and a first input of a second adder. A quantization signal is produced in response to the first adder and applied to an LSB of a second input of the second adder, which produces an error signal representing the difference between the quatization signal and the error feedback signal. The error signal is delayed a predetermined amount to produce the error feedback signal, wherein energy of the quantization signal is spread over a broad frequency spectrum between DC and F
S
/2. A pair of out-of-phase, non-overlapping chopping signals are produced in response to the quantization signal and applied to the chopping signals to corresponding chopper switches of the chopper stabilized amplifier.
In another embodiment, a delta-sigma modulator includes a switched capacitor feedback reference voltage sampling circuit, an integrator, a comparator, a switched capacitor input sampling circuit, a plurality of chopper stabilization input switches coupling the switched capacitor input sampling circuit to an input of the integrator, a plurality of chopper stabilization output switches coupling an output of the integrator to an input of the comparator, and a frequency-shaped pseudo-random chopper clock signal generator circuit. The frequency-shaping pseudo-random chopper clock signal generator circuit includes a pseudo-random sequence generator and a digital delta-sigma modulator. The digital delta-sigma modulator includes a feedback delay circuit and a first digital adder receiving as inputs a pseudo-random sequence signal produced by the pseudo-random sequence generator and an error feedback signal produced by the feedback delay circuit. A 1-bit quantizer produces a frequency-shaped pseudo-random clock signal in response to the pseudo-random sequence signal and the error feedback signal. A second digital adder produces a digital error signal as an input to the feedback delay circuit in response to the frequency-shaped pseudo-random clock signal and the error feedback signal. A logic circuit produces complementary, non-overlapping chopper clock signals in response to the frequency-shaped pseudo-random clock signal. The complementary, non-overlapping chopper clock signals are applied to control various ones of the chopper stabilization input switches and chopper stabilization output switches.
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Bocure Tesfaldet
Burr-Brown Corporation
Cahill Sutton & Thomas P.L.C.
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