Oscillators – Plural oscillators – Selectively connected to common output or oscillator...
Reexamination Certificate
1999-06-23
2001-01-23
Kinkead, Arnold (Department: 2817)
Oscillators
Plural oscillators
Selectively connected to common output or oscillator...
C331S055000, C331S074000, C331S002000, C327S141000, C327S144000, C327S145000, C327S146000
Reexamination Certificate
active
06177845
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a frequency-providing circuit
BACKGROUND OF THE INVENTION
FIG. 1
shows a frequency-providing circuit
10
, as known in the art, which is typically employed in instruments such as pulse or pattern generators. The frequency-providing circuit
10
comprises an oscillator
20
with a certain frequency range f
min
to f
max
, an output thereof being coupled via a line
25
to a frequency divider circuit
30
. The frequency divider circuit
30
is used to divide an output frequency f
osc
of the oscillator
20
on line
25
to an output frequency f
out
<f
min
. For setting the output frequency f
out
, the oscillator
20
receives an oscillator control signal on a line
40
and the frequency divider circuit
30
receives a divider control signal on a line
50
.
The range of the output frequency f
out
can be provided in several sub-ranges in accordance with a selected divide factor DF provided by the divider control signal on line
50
to the frequency divider circuit
30
. In case that the frequency range of the oscillator
20
is e.g. f
min
:f
max
=1:2 with f
max
=100 MHz, the range of the output frequency f
out
can be provided in several sub-ranges as depicted in the below table:
DF
f
out
Sub-range 1
1
50.00 . . . 100.0 MHz
Sub-range 2
2
25.00 . . . 50.00 MHZ
Sub-range 3
3
12.50 . . . 25.00 MHz
Sub-range n
n
50/2
n
. . . 100/2
n
MHz
When the output frequency f
out
is to be changed, the oscillator
20
receives a specified oscillator control signal
40
and the frequency divider circuit
30
a specified divider factor DF on line
50
.
FIGS.
2
a
and
2
b
show examples wherein the output frequency f
out
is to be changed. In FIG.
2
a,
the output frequency f
out
is to be changed from a frequency f
old
to a new frequency f
new
, whereby the two frequencies f
old
and f
new
are within one sub-range. The oscillator
20
sweeps between corresponding oscillator frequencies f
osc—old
to f
osc—new
within a certain settling time, usually in the range of microseconds up to milliseconds. During that settling time, the output frequency f
out
changes continuously from f
old
to f
new
and is always somewhere between f
old
and f
new
.
In FIG.
2
b
, the two output-frequencies f
old
and f
new
are in different sub-ranges. The oscillator
20
has to be programmed to a new frequency and the frequency divider circuit
30
has to change the divide ratio. Changing the divider factor DF can happen from one clock period to another while changing the oscillator frequency f
osc
takes some more time (cf. FIG.
2
A). That means that, at the beginning of a change in the output frequency f
out
, the oscillator frequency still remains at the value f
osc—old
while the divider factor DF has been changed from an old divider factor DF
old
to a new divider factor DF
new
. Thus, the output frequency f
out
is immediately changed from a value f
out
=f
osc—old
/DF
old
to a value f
out
′=f
osc—old
/DF
new
, whereby the value f
out
′ can exceed the range between the two output-frequencies f
old
and f
new
. In FIG.
2
b
, the output frequency f
out
is first changed between two sub-ranges from f
old
to f
new
and then back to f
old
. In contrast to FIG.
2
a
, the output frequency f
out
exceeds the range between f
old
and f
new
during the respective settling time of the oscillator
20
.
As well in the case of FIG.
2
a
as in case of FIG.
2
b
it is impossible to provide a new output frequency f
out
without getting ‘wrong’ frequencies during the settling time of the oscillator
20
. This in particular undesirable when testing the dynamic behavior of circuits like Phase Locked Loops (PLLS) or clock recovery circuits.
A more severe problem, however, occurs in the case of FIG.
2
b
wherein the output frequency f
out
exceeds the frequency range between f
old
and f
new
during the settling time. This is in particular unacceptable, for example, when a user wants to check an upper operating limit of a circuit, since the frequency change can lead to a much higher frequency than desired. The test circuit can thus produce failures during the settling time or can get out of lock.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved frequency-providing circuit. This object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.
According to the invention, a frequency-providing circuit for providing an output signal at a frequency f
out
comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency f
osc
, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency f
out
of the output signal can be changed, with respect to the frequency f
osc
, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.
Another frequency-providing circuit according to the invention comprises a first and a second oscillator, a frequency-selecting unit, and the frequency-changing circuit. The first oscillator receives a first oscillator control signal and provides a first frequency output at a first oscillator frequency f
oscA
. The second oscillator receives a second oscillator control signal and provides a second frequency output at a second oscillator frequency f
oscB
. The frequency-selecting unit receives as inputs the first and second frequency outputs and is controlled by a frequency-selecting control signal for selecting one of the inputs as an output The frequency-changing circuit receives the output of the frequency-selecting unit at a first input and a frequency-changing control signal at a second input and derives the output signal therefrom, whereby the frequency f
out
of the output signal can be changed with respect to the frequency f
osc
in accordance with the setting of the frequency-changing control signal.
The invention thus allows an improved switching between different frequencies.
For reducing or avoiding a shift in phase of the output signal when switching between different frequencies, a synchronizing of the switching between the oscillator frequencies has to be provided. The synchronizing circuit therefore preferably comprises means for disabling an application of a successive frequency-selecting control signal and or frequency-changing control signal until the phases of the oscillator frequencies match within a given range.
REFERENCES:
patent: 4259744 (1981-03-01), Junod et al.
patent: 5075640 (1991-12-01), Miyazawa
patent: 5487093 (1996-01-01), Adresen et al.
patent: 5757240 (1998-05-01), Boerstler et al.
patent: 0345940A2 (1989-02-01), None
European Search Report, EP 98 11 2853 Nov. 18, 1998.
IEEE 1993 Custom Integrated Circuits Conference, Sep. 5, 1993, pp. 4.4.1-4.4.4, Junichi Goto et al., “A Programmable Clock Generator With 50 to 350 MHz Lock Range for Video Signal Processors”.
Hewlett -Packard Company
Kinkead Arnold
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