Frequency offset correction circuit device

Details Frequency offset correction circuit device Frequency offset correction circuit device

2005-09-07

2009-06-02

Payne, David C (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S316000, C375S317000

Reexamination Certificate

active

07542527

ABSTRACT:
A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S11) obtained by performing digital processing on an output signal (S6) from an AD converter (6), the maximum value (S12) and the minimum value (S13) are detected as digital values by a maximum value holding circuit (11) and a minimum value holding circuit (12), an averaging circuit (13) obtains an average value (intermediate value) of the maximum value and the minimum value and detects a frequency offset amount (S14), and the frequency offset amount is fed back to a threshold value of data decision (14), so that binarized demodulation data (S15) is outputted in which the offset of the demodulation baseband signal is corrected.

REFERENCES:
patent: 5438692 (1995-08-01), Mohindra
patent: 5970397 (1999-10-01), Klank et al.
patent: 6633752 (2003-10-01), Hashigaya
patent: 6731698 (2004-05-01), Yoshie
patent: 2004/0190650 (2004-09-01), Korram et al.
patent: 2004/0264582 (2004-12-01), Mauritz et al.

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