Frequency multiplying system having a plurality of output...

Details Frequency multiplying system having a plurality of output... Frequency multiplying system having a plurality of output...

2002-10-16

2003-12-23

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S158000

Reexamination Certificate

active

06667639

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a frequency multiplying system having a plurality of output frequencies and, more particularly, to a frequency multiplying system for generating a plurality of multiple-frequency signals based on an input reference-frequency signal.
(b) Description of the Related Art
A frequency multiplying system having a plurality of output frequencies is used in the field of computer systems for generating one or more multiple-frequency clocks having a frequency equal to or multiplied from a reference frequency of an input reference clock, the multiple frequency being generally 2
n
times as high as the reference frequency, where given n is an integer including zero. Such a frequency multiplying system, which may be called herein multiple-frequency clock generator, is generally implemented by a phase locked loop (PLL) circuit.
FIG. 12
shows the configuration of a conventional multiple-frequency clock generator or PLL circuit. The conventional PLL circuit
200
includes a frequency multiplier
201
, a delay circuit
202
, a phase comparator
203
, and three frequency dividers
204
,
205
and
206
. The frequency multiplier
201
multiplies the reference frequency of an input reference clock CLK
10
to generate an internal clock CLK
20
, which is fed through the delay circuit
202
to each of the frequency dividers
204
,
205
and
206
while being introduced with a delay time.
Each frequency divider
204
,
205
or
206
divides the delayed internal clock to generate a multiple-frequency clock having a specified multiple frequency. In this example, the frequency divider
204
generates a quadruple-frequency clock CLK
14
, the frequency divider
205
generates a double-frequency clock CLK
12
, and the frequency divider
206
generates an equal-frequency clock CLK
11
, wherein all these clocks having frequencies defined in terms of the reference frequency are output from the PLL circuit
200
.
One of the output clocks CLK
14
, CLK
12
, CLK
11
from the frequency dividers
204
,
205
and
206
which has a period equal to or longer than the period of the reference frequency, namely the output clock CLK
11
in this example, is fed-back as a feedback clock to the phase comparator
203
to form a feedback loop. The phase comparator
203
compares the phase of the feedback clock CLK
11
against the phase of the reference clock CLK
10
by using the rising edge of the reference clock CLK
10
, thereby determining the delay time to be effected by the delay circuit
202
. The delay circuit
202
has a plurality of delay elements each for introducing a unit delay time, and determines a desired delay time by selecting a number of the delay elements. By introducing a suitable delay time to the multiple-frequency internal clock CLK
20
in the delay circuit
202
, the PLL circuit
200
is locked with the reference clock CLK
10
, wherein the multiple-frequency clocks CLK
11
, CLK
12
and CLK
13
are all in synchrony with the reference clock CLK
10
.
FIGS. 13A and 13B
are timing charts (or waveform diagrams) showing the timing relationships between the reference clock CLK
10
and the multiple-frequency clocks CLK
11
, CLK
12
and CLK
14
, at the timing of the phase comparison (in
FIG. 13A
) and at the timing after the locking (in FIG.
13
B). At the start for the locking operation, as shown in
FIG. 13A
, the feedback clock CLK
15
lags by a time length t
12
with respect to the reference clock CLK
10
in terms of the rising edges of the reference clock CLK
10
and the feedback clock CLK
15
. The phase comparator
203
controls the delay circuit
202
to introduce a desired delay time to the internal clock CLK
20
so that the rising edge of the feedback clock CLK
15
approaches the rising edge of the reference clock CLK
10
.
By iterating the phase comparison of both the rising edges and the delay control of the delay circuit
202
so as to introduce a suitable delay time to the internal clock CLK
20
, the phase comparator
203
allows the PLL circuit
200
to be locked with the reference clock CLK
10
, after the delay time introduced by the delay circuit
202
equals a time length t
22
to obtain a synchrony of both the rising edges. After the locking, the phases of the multiple-frequency clocks CLK
11
, CLK
12
and CLK
14
which are obtained by diving the internal clock CLK
20
are in synchrony with the phase of reference clock CLK
10
, as shown in FIG.
13
B.
It is to be noted that the achievement of locking by the PLL circuit
200
means that the phase difference between the reference clock CLK
10
and the internal clock CLK
20
resides within an allowable error range. More specifically, a more detailed comparison while enlarging the time axis would find a small phase difference corresponding to the error between both the clocks CLK
10
and CLK
20
. In addition, there is also a small phase difference between each two of the multiple-frequency clocks CLK
11
, CLK
12
and CLK
14
obtained by dividing the delayed internal clock. These small phase differences may cause a problem especially in the quadruple-frequency clock CLK
14
, although the small phase difference causes a substantially little problem in the equal-frequency clock CLK
11
, in view of the short period of the quadruple-frequency clock CLK
14
. In this respect, there is a possibility that the phase difference between the reference clock CLK
10
and the quadruple-frequency clock CLK
14
may be a sum of the maximum phase error between the reference clock CLK
10
and the feedback clock CLK
15
and the maximum phase error between the feedback clock CLK
15
and the quadruple-frequency clock CLK
14
.
In the PLL circuit
200
of
FIG. 12
, the delay control range in the delay circuit
202
should correspond to the single period of the reference clock CLK
10
, and thus the delay circuit
202
includes a plurality of delay elements for introducing a delay of the delay control range corresponding to the single period of the reference clock CLK
10
. If the number of the delay elements in the delay circuit
202
is large, however, the delay circuit
202
has a corresponding large occupied area. In addition, if the reference clock CLK
10
has a large period which corresponds to a plurality of unit delay times, a larger number of the delay elements further increase the occupied area of the delay circuit
202
. Furthermore, a larger delay control range means that a larger locking time is needed in the PLL circuit
200
.
If another of the multiple-frequency clocks CLK
12
and CLK
14
having a smaller period than the output clock CLK
11
is employed as the feedback clock
15
, the phase error may include only the phase difference between the another of the multiple-frequency clocks CLK
12
and CLK
14
and the reference clock CLK
10
.
FIGS. 14A and 14B
show the timing charts, similarly to
FIGS. 13A and 13B
, respectively, in the case wherein the quadruple-frequency clock CLK
14
is employed as the feedback clock CLK
15
.
It is assumed that the feedback clock CLK
15
has a delay time t
13
with respect to the reference clock CLK
10
, as shown in
FIG. 14A
, at the timing of the phase comparison, i.e., the start of the locking operation. After the phase comparison, a delay time is introduced to the feedback clock CLK
15
so that the rising edge of the feedback clock CLK
15
leading from and nearest to the rising edge of the reference clock CLK
10
coincides with the rising edge of the reference clock CLK
10
. After a delay time corresponding to the time length t
33
is introduced to the feedback clock CLK
15
, the PLL circuit
100
is locked with the reference clock CLK
10
. In this case, the delay control range corresponds to the period of the quadruple-frequency clock CLK
14
.
After the locking of the feedback clock CLK
15
with the reference clock CLK
10
, however, the phase of the equal-frequency clock CLK
11
deviates from the phase of the reference clock CLK
10
by a half period in terms of the reference clock CLK
10
although the multiple-frequency clocks CLK
1

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