Frequency multiplying delay-locked loop

Details Frequency multiplying delay-locked loop Frequency multiplying delay-locked loop

2006-11-22

2009-02-24

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

07495489

ABSTRACT:
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.

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patent: 6380811 (2002-04-01), Zarubinsky et al.
patent: 6784707 (2004-08-01), Kim et al.
patent: 6906566 (2005-06-01), Drexler
patent: 6930524 (2005-08-01), Drexler

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