Frequency multiplying clock signal generator

Details Frequency multiplying clock signal generator Frequency multiplying clock signal generator

1994-05-25

1995-12-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327113, 327175, 327172, 377 47, H03B 1900, H03K 3017

Patent

active

054791251

ABSTRACT:
A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.

REFERENCES:
patent: 4613775 (1986-09-01), Dick
patent: 4691330 (1986-09-01), Takahashi et al.
patent: 4799022 (1989-01-01), Skierszkan
patent: 5101419 (1992-03-01), Lowe et al.

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