Frequency multiplier pre-stage for fractional-N phase-locked...

Details Frequency multiplier pre-stage for fractional-N phase-locked... Frequency multiplier pre-stage for fractional-N phase-locked...

2007-11-13

2007-11-13

Orgad, Edan (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S255000, C455S257000, C455S264000, C455S265000, C331S053000

Reexamination Certificate

active

10964865

ABSTRACT:
A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

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Hyungki Huh, et al.; “A CMOS Dual Band Fractional-N Synthesizer with Reference Doubler and Compensated Charge Pump”; IN: IEEE Intern Solid-State Circuits Conf., Feb. 15-19, 2004, vol. 1, Chapter 5.6.
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