Frequency multiplier for controlling pulse width within a prescr

Details Frequency multiplier for controlling pulse width within a prescr Frequency multiplier for controlling pulse width within a prescr

1997-12-11

1999-11-30

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327119, 327122, H03B 1900

Patent

active

059949309

ABSTRACT:
A frequency multiplier for controlling a pulse width maintains a desired pulse width irrespective of a semiconductor fabrication process variation. The multiplier includes a delay unit for delaying an input signal and an exclusive OR-gate for exclusively ORing the delayed signal from the delay unit and the input signal. The multiplier further includes inverters that sequentially invert the signal from the exclusive OR-gate and a low-pass filter that filters the signal from the exclusive OR-gate. A high electric potential comparator and low electric potential comparator are for comparing the signal from the low-pass filter with first and second voltage limits to output first and second switch control signals to the delay unit, respectively.

REFERENCES:
patent: 5010561 (1991-04-01), Itoh
patent: 5297179 (1994-03-01), Tatsumi
patent: 5514990 (1996-05-01), Mukaine et al.
Woeste, Dana et al., "FA 8.4: Digital-Phase Aligner Macro for Clock Tree Compensation with 70ps Jitter", 1996 IEEE International Solid-State Circuits Conference, Feb. 9, 1966, pp. 136-137.

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