Frequency multiplier circuitry and method

Details Frequency multiplier circuitry and method Frequency multiplier circuitry and method

1989-03-31

1990-07-10

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377 47, H03K 2140

Patent

active

049411608

ABSTRACT:
Generally there is provided circuitry and a method for frequency multiplication of a first signal source including a first counter for counting pulses from a second signal of higher frequency by counting from a loaded value and generating a circuit output each time the first counter resets. A second counter is used to count cycles of the first counter and generate a feedback signal when a predetermined number of cycles have been completed (the system multiplication factor). Calibration is achieved by comparing the end of the period of the first signal to the occurrence of a feedback signal. In response the comparision circuit causes the loaded value to be changed to thereby control the output.

REFERENCES:
patent: 4017719 (1977-04-01), Kaplin et al.
patent: 4086471 (1978-04-01), Takahashi
patent: 4115687 (1978-09-01), Boese et al.
patent: 4339722 (1982-07-01), Sydor et al.
patent: 4773031 (1988-09-01), Tobin

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